Senior Manager, Mixed-Signal and Systems Validation

Broadcom•San Jose, CA

1d•$167,500 - $268,000

About The Position

We are seeking a highly technical Senior Manager to lead a world-class engineering team responsible for the post-silicon validation, mixed-signal IP verification, and system-level testing of next-generation Hard Disk Drive (HDD) Read Channels and advanced AI ASICs. In this role, you will bridge the gap between silicon design and system deployment. You will work with the team to develop test strategies for the HDD read channel, mixed-signal IPs—including high-speed ADCs, PLLs, and feedback loops— and AI ASICs to ensure the systems meet the required standards of performance, reliability, and quality.

Requirements

Master’s (MS) or Ph.D. in Electrical Engineering, Computer Engineering, or a closely related technical field.
15+ years of experience in read channel/HDD design/validation, post-silicon validation, mixed-signal IC characterization, or system engineering.
5+ years managing technical team of engineers.
Proven track record of managing, leading, and building high-performing technical engineering teams.
Deep understanding of HDD architectures , signal processing, and Read Channel technologies and systems validation.
Strong technical understanding of ADCs, PLLs, Continuous-Time Filters, and closed-loop feedback systems.
Understanding AI/ML ASICs and accelerators .
Strong expertise in System-Level Testing (SLT) , board-level debugging, and lab equipment (oscilloscopes, logic analyzers, protocol analyzers).
Proficient in test automation languages (e.g., Python , MATLAB) and lab equipment automation.
Strong data analysis skills to interpret complex silicon characterization data.
Excellent communication and presentation skills, with the ability to translate complex technical concepts for executive leadership and stakeholders.
Strong problem-solving skills and a data-driven approach to debugging and decision-making.

Responsibilities

Manage and mentor a talented team of validation and system integration engineers, fostering a culture of innovation, accountability, and continuous growth.
Oversee project scheduling, resource planning, and budget management to ensure milestones are met on time and within scope.
Partner closely with ASIC Design, Architecture, Firmware, and Product Engineering teams to align on validation requirements and resolve complex technical issues.
Define and execute comprehensive pre-silicon and post-silicon validation plans for complex HDD Read Channels and high-performance AI ASICs. Pre-silicon validation is accomplished with Palladium and Zebu emulators, post silicon validation is on the ASICs using test systems designed for the devices.
Lead the bring-up, characterization, and debugging of new silicon in the lab, identifying and root-causing hardware and architectural flaws.
Drive the development of scalable, automated test infrastructure and methodologies to improve test coverage and execution efficiency.