Senior Manager, Analog & Mixed-Signal Design Engineering

Intel Corporation•Chandler, AZ

23h•$164,470 - $269,100•Onsite

About The Position

The Hard IP and Test Chip Development team within Intel's Central Engineering Group (CEG) is responsible for delivering industry-leading analog and mixed-signal IP for Intel's Client, Data Center, AI, and Foundry businesses. The I/O team develops high-speed serial I/O and die-to-die interconnect solutions across advanced process technologies, enabling next-generation computing platforms. As a Senior Manager, Analog & Mixed-Signal Design Engineering, you will lead a team responsible for developing cutting-edge analog IP and silicon solutions that shape Intel's future in high-speed connectivity, chiplet architectures, and advanced interconnect technologies. This is a highly visible leadership role offering the opportunity to influence critical technologies, partner across multiple engineering organizations, and drive execution on products that are foundational to Intel's future. Candidates will gain exposure across the complete product lifecycle, from architecture and design through silicon validation and production readiness, while helping grow and develop a team of talented engineers.

Requirements

Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 9+ years of experience.
6+ years of experience in a people leadership, technical leadership, project leadership, or management role within a matrixed organization.
8+ years of experience delivering analog or mixed-signal IP from concept through silicon validation and product deployment.
7+ years of experience with analog design fundamentals, including noise, jitter, matching, stability, linearity, and/or performance optimization
7+ years of experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.

Nice To Haves

Master's degree in Electrical Engineering, Electronics Engineering, or related field with 6+ years of experience.
Experience managing analog IP design teams.
Experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, Transmitter (TX) design, or Receiver (RX) design.
Knowledgeable about high speed serial IO technologies such as PCIe/CXL and USB Type C and of die to die technologies such as UCIe.
Building, leading, and driving execution in silicon teams delivering to complex, high-impact programs.

Responsibilities

Lead the development and delivery of analog and mixed-signal IP including ADCs, DACs, phase interpolators, voltage regulators, clocking circuits, and other high-performance analog building blocks.
Drive technical excellence throughout the product lifecycle, including architecture reviews, design execution, verification, silicon bring-up, validation, and product readiness.
Partner with senior technical leaders to establish technical direction and align organizational priorities with product roadmaps.
Promote engineering innovation through automation, process optimization, and AI-assisted engineering methodologies.
Develop execution strategies and project plans that enable successful delivery of IP and SoC milestones.
Manage schedules, resources, risks, dependencies, and deliverables across multiple concurrent development efforts.
Leverage data-driven insights to communicate progress, support decision-making, and drive successful business outcomes.
Ensure alignment across geographically distributed teams and stakeholders.
Build, lead, and develop a high-performing organization of analog and mixed-signal design engineers.
Recruit, coach, mentor, and retain top engineering talent.
Foster an inclusive culture that promotes innovation, collaboration, accountability, and continuous learning.
Develop future technical and organizational leaders through active coaching and professional development.
Partner closely with architecture, design, validation, physical design, layout, product engineering, manufacturing, and program management teams.
Collaborate across Intel organizations to deliver complete end-to-end solutions and drive successful product outcomes.
Work with global engineering teams, including collaboration across U.S. and India-based partners, to achieve shared goals and execution milestones.
Drive organizational excellence through strong leadership, execution discipline, and operational rigor.
Influence strategic decisions while balancing technical, business, and organization priorities.
Help shape future technology directions that enable Intel's next generation of AI, client, datacenter, and foundry solutions.