Senior Manager, Analog Methodology & AI Innovation

Synopsys • Boxborough, MA

8d • $175,000 - $263,000 • Onsite

About The Position

At Synopsys, our Silicon IP business is expanding to serve growing demand for special-purpose silicon. We are moving beyond traditional standards-based IP into application-optimized IP (AOIP), helping customers develop differentiated silicon tailored to specific workloads and system architectures. As AI drives demand for custom silicon across hyperscalers and system companies, we use our interface IP leadership, system expertise, and engineering scale to deliver optimized IP subsystems and platforms that accelerate time-to-market while improving performance and efficiency. The acceleration of frontier intelligence is fueling an unprecedented demand for compute power while increasing system complexity, and purpose-built silicon is reshaping the IP market.

You are an experienced and passionate Analog Methodology Engineer with a deep understanding of mixed-signal circuit design principles and emerging AI/ML technologies. You thrive in a collaborative environment and work well with a cross-functional team of experts. Your hands-on experience with transistor-level simulation, reliability analysis, and static timing analysis (STA) sets you apart. You are proficient in scripting and automation, and you use those skills to streamline design processes and mentor other engineers. You apply AI and machine learning to analog circuit optimization, your knowledge spans analog and mixed-signal circuits, and you have a strong background in silicon IP release requirements. You are also credible with customers, product teams, and foundries, and you can turn methodology strategy into decisions other organizations will adopt. Your communication is clear, and you are self-motivated, detail-oriented, and committed to excellence.

The Analog Integration Team (AIT) exists to coordinate and accelerate methodology adoption across analog and adjacent engineering domains, including circuit-to-layout, circuit-to-timing, silicon-to-lab correlation, SI/PI integration, and other mixed-signal cross-domain workflows. In this role, you will:

Provide clear ownership for analog and adjacent-domain methodology areas.
Act as the focal point for customer-driven methodology requirements and integration challenges.
Be accountable for prioritization, adoption, stakeholder engagement, and execution.
Improve coordination across product teams and adjacent engineering organizations, including engagement with customers and foundries.
Support methodology for application-optimized IP and the special-purpose silicon customers are building for specific workloads and system architectures.

The Impact You Will Have:

Establish sustainable ownership for analog and adjacent-domain methodologies.
Improve responsiveness to customer methodology requirements.
Reduce ambiguity on methodology ownership and escalation paths.
Improve alignment between methodology strategy and execution.
Accelerate methodology adoption for strategic initiatives and customers, including application-optimized IP for special-purpose silicon.
Provide measurable accountability for methodology development, deployment, and customer engagement.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar technical field; MSEE or PhD preferred.
• 18-25 years of experience in IC design with a BSEE degree, or 15-18 years with an MSEE or PhD.
• Extensive knowledge of analog design methodology and of several related areas, including simulation methodology and other mixed-signal methodology domains.
• Strong command of transistor-level design, CMOS fundamentals, reliability effects, and SPICE-based verification, deep enough to direct methodology execution.
• Experience running analog design methodology execution for special-purpose silicon tailored to specific workloads and system architectures.
• Enough depth in adjacent analog methodology areas to represent that work with partner teams.
• Manage analog design and/or analog methodology resources, with accountability for staffing, methods, budgets, schedules, and results.
• Oversee operational and functional objectives, and contribute to short-term operational plans with measurable results for the department.
• Address complex issues and implement policies and evaluation criteria that support broader business change when necessary.
• Primary customer interface for analog design methodology execution.
• Work with senior management across several functions, and with product, program, and go-to-market partners on planning and execution.
• Influence others in sensitive situations. That includes partner teams that own methodology outside your group’s direct competency, and technology and other organizations outside the IP group.

Nice To Haves

• MSEE or PhD preferred.

Responsibilities

• Provide clear ownership for analog and adjacent-domain methodology areas.
• Act as the focal point for customer-driven methodology requirements and integration challenges.
• Be accountable for prioritization, adoption, stakeholder engagement, and execution.
• Improve coordination across product teams and adjacent engineering organizations, including engagement with customers and foundries.
• Support methodology for application-optimized IP and the special-purpose silicon customers are building for specific workloads and system architectures.
• Establish sustainable ownership for analog and adjacent-domain methodologies.
• Improve responsiveness to customer methodology requirements.
• Reduce ambiguity on methodology ownership and escalation paths.
• Improve alignment between methodology strategy and execution.
• Accelerate methodology adoption for strategic initiatives and customers, including application-optimized IP for special-purpose silicon.
• Provide measurable accountability for methodology development, deployment, and customer engagement.

Benefits

• Inclusive work culture supporting diverse backgrounds and experiences.
• Reasonable accommodations available throughout the recruitment and employment process.
• Annual bonus
• Equity
• Other discretionary bonuses
• Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior