Senior Manager, Analog Layout Design
About The Position
As an Analog Layout Manager with Marvell, you’ll be a member of the Central Engineering business group. You’ll be part of a small analog team making a big impact on this organization. Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects. We are seeking an experienced Analog Layout Senior Manager to lead and grow a team of analog layout engineers responsible for delivering high-quality physical layout solutions for high-speed, mixed-signal, and advanced technology integrated circuits products. This role combines technical leadership, people management, project execution, and methodology development to ensure successful delivery of complex semiconductor products across multiple technology nodes and product generations. The ideal candidate possesses deep expertise in analog and mixed-signal layout design, strong leadership skills, and a proven track record of delivering successful tapeouts in advanced process technologies.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field.
- 10+ years of analog layout design experience, including 3+ years in a leadership role managing teams, projects, or technical execution.
- Strong hands-on expertise in advanced analog, high-speed, and mixed-signal layout design, with experience in circuits such as SerDes, PLLs, ADCs/DACs, TIAs, drivers, clocking, power management, and other mixed-signal blocks.
- Deep understanding of semiconductor devices, process technologies, parasitics, matching, shielding, isolation, reliability, manufacturability, and physical design best practices.
- Proficiency with industry-standard EDA tools, including Cadence Virtuoso, Calibre, PVS, StarRC, or equivalent.
- Experience with advanced FinFET process nodes and a proven track record of multiple successful tapeouts.
- Demonstrated ability to lead, mentor, and scale high-performing engineering teams while driving layout methodology, automation, productivity improvements, and technical excellence.
- Strong project management, prioritization, problem-solving, decision-making, communication, and collaboration skills, with the ability to influence and work effectively across cross-functional and global engineering teams.
Responsibilities
- Lead, mentor, and develop a high-performing team of analog layout engineers through technical coaching, performance management, career development, and succession planning.
- Foster a culture of ownership, accountability, collaboration, innovation, and technical excellence.
- Drive hiring, onboarding, retention, and growth of top engineering talent while developing future technical and organizational leaders.
- Provide clear direction, motivation, and support to enable team success and continuous professional development.
- Own layout execution planning, resource allocation, schedule management, and quality delivery across multiple projects.
- Ensure timely completion of layout milestones while maintaining high standards of quality and design integrity.
- Partner with program management and engineering leadership to identify risks, establish priorities, and drive project execution.
- Provide technical guidance for analog and mixed-signal layout implementation in advanced technologies, including FinFET, CMOS and BiCMOS processes.
- Oversee layout development for high-speed and mixed-signal circuits.
- Lead layout reviews to ensure compliance with design requirements, foundry rules, reliability standards, and industry best practices.
- Drive robust implementation of matching, shielding, isolation, noise mitigation, electromigration, EM/IR, ESD protection, and manufacturability considerations.
- Collaborate closely with circuit design, physical design, CAD, verification, reliability, and program management teams throughout the product development cycle.
- Support debugging, silicon bring-up activities, root-cause analysis, yield improvement initiatives, and post-tapeout issue resolution.
- Facilitate effective communication and alignment across geographically distributed engineering teams.
- Drive improvements in layout methodologies, automation, reusable IP strategies, verification flows, and overall execution efficiency.
- Establish and maintain layout design standards, review processes, checklists, and best practices.
- Evaluate and deploy new EDA technologies, tools, and workflow enhancements to improve efficiency and design quality.
- Stay current with emerging semiconductor technologies, industry trends, and layout methodologies.
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Senior
