Senior Manager - Analog Design

Advanced Micro Devices, Inc•Boxborough, MA

7d•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. AMD seeks a candidate who will be managing the Memory I/O design team supporting the definition, specification, system simulation and implementation of future LPDDR IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration, equalization; and development of abstracted models for link performance simulations.

Requirements

Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation.
Strong/effective communication skills and enthusiastic team-first mentality.
Minimum 5+ years of team management experience leading multiple IPs from design to production

Nice To Haves

A proven track record of successfully leading execution of multiple PHY designs with very good Silicon results.
A proven successful track record in circuit-architecture and modeling for High Speed IOs
Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
Ability to dig into RTL or FW code supporting the custom circuit implementation

Responsibilities

Manage and contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHYs
Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
Manage execution and deliverables across customers and stakeholders
Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
Participate and contribute to the definition of development flows that improve efficiency and quality of execution