Senior Integrated Circuit Wafer Probe Hardware Design & Validation Engineer (Probe Specialist)

Broadcom•San Jose, CA

5d•$143,800 - $230,000

About The Position

We build some of the largest, highest-power silicon in the industry – full reticle (~850 mm2) 2.5D/3D devices dissipating multiple kilowatts, with tens of thousands of contacts, high-current power delivery, and 100G+ I/O. Testing these parts at wafer sort, final package, and system level pushes past where standard methods work: probe-tip planarity and CTE walk across the reticle, IR drop through the needle interface, thermal gradients that move everything, and coverage that has to be split intelligently across ATE and SLT. We are seeking a highly specialized Senior Probe Hardware Design & Validation Engineer who gets ahead of these problems rather than reacting to them – someone who serves as our subject matter expert (SME) in next-generation probing technologies. In this role, you will own the entire lifecycle of custom probe architectures — from initial electric, thermal and mechanical modeling to probe hardware design, supplier oversight, technology proof in and production issue debug. You will bridge the gap between design simulation and real-world silicon/hardware testing, ensuring our high-density, high- power probing solutions deliver flawless signal integrity and mechanical reliability under extreme testing conditions for probing full reticle size die for our custom AI products.

Requirements

Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, or a related discipline.
12+ years of hands-on experience specifically focused on probe card design, vertical/MEMS probes, or high-performance test fixture development.
Strong hands-on experience using Vector Network Analyzers (VNAs), Time-Domain Reflectometry (TDR), and scopes to analyze SI and PI performance.
Deep understanding of transmission line theory, RF/microwave principles, and signal/power integrity (SI/PI) fundamentals.
High proficiency with 3D CAD software (SolidWorks, Autodesk Inventor, or Creo) and FEA modeling techniques.

Nice To Haves

Experience with production wafer prober or singulated die prober with ATE is highly desirable.
Familiarity with semiconductor wafer sort processes or automated test equipment (ATE) platforms (e.g., Advantest, Teradyne).
Knowledge of metallurgy, micro-plating, or advanced materials science relevant to probe tip wear and contact physics.
Experience with scripting languages (Python, MATLAB) and AI tools to automate data collection and analysis during validation loops.

Responsibilities

Lead the mechanical and electrical architecture of advanced probe cards with vertical probe, MEMS probe, direct dock, probe on micro-bump, probe on sacrificial pad, and space transformer, and probe card PCB Signal Integrity (SI) and Power Integrity (PI) Analysis.
Performability to simulate and optimize SI with impedance and crosstalk control, and optimize PI with power plane and decoupling cap using frequency domain PDN analysis.
Evaluate mechanical contact force distribution, probe alignment and planarity, warpage from thermal expansion mismatch across temperature.
Architect and evaluate probe solutions for wafer probes, 3D IC subassembly probe and singulated die probing, probe performance analysis (C_res, CCC, probe mark size and touchdown life span), cooling capability and warpage profile.
Utilize advanced lab equipment (TDR oscilloscopes, VNAs, microscopes, and wafer probers) to quantify hardware performance.
Drive failure analysis (FA) investigations for probe wear, probe burn, prober planarity and optical alignment issues, implementing corrective design actions.
Partner closely with external probe and probe card design companies.
Work alongside Test Engineering, Product Engineering, and IC Design teams to ensure probe capabilities align with product roadmaps and test floor requirements.