Senior I/O Subsystem Architect

NVIDIA•Santa Clara, CA

1d•Hybrid

About The Position

We are now looking for a Senior I/O Architect for our NVLink chip to chip team! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols. You’ll be part of a team responsible for defining next generation communications standards and products building on our current NVLink technology. The job scope ranges from developing initial product requirements, working with research, other architects, software/firmware and product development teams to shepherd the design through all phases of the product lifecycle. What you will be doing: Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip Architectural modeling, validation, definition and documentation Driving implementation across design, verification, firmware and software teams Working with various teams to define NVLink C2C architecture NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you! #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 224,000 USD - 356,500 USD for Level 5, and 272,000 USD - 431,250 USD for Level 6. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until February 3, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Requirements

MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience)
10+ years of relevant experience in some combination of architecture, design, and verification
Proven experience over link layer architecture (Transaction layer, Data link layer, Physical layer)
Experience with existing interconnects (PCIE, UCIE, Chip to Chip links) and knowledge of Industry standard protocols CHI/CXL/AXI
Able to define system architecture with NVLINK-C2C interconnects and SW stack around it
Collaborate with multi-functional teams including IP, SoC, physical/package design, firmware, electrical design, and validation to drive interconnect technology development and integration
Evaluate and trade off technical solutions to meet platform requirements for current and future products
Have completed and shipped multiple projects and are skilled at I/O Architecture
Experience leading projects from concept through product lifecycle, including pathfinding, prototyping, and deployment

Responsibilities

Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip
Architectural modeling, validation, definition and documentation
Driving implementation across design, verification, firmware and software teams
Working with various teams to define NVLink C2C architecture