SoC Architect (Memory Subsystem)

Samsung•San Jose, CA

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a SoC Architect (Memory Subsystem), you will define and drive the architecture of SoC memory and cache subsystems for Samsung’s premium chipsets, with a strong focus on enabling on-device machine learning. In this high-impact, highly visible role, you will identify and analyze emerging use cases, propose innovative memory architectures, and experiment with new ideas in collaboration with global cross-functional teams. Your deep expertise in SoC architecture, cache hierarchy, and memory subsystems will fuel innovation for cutting-edge memory solutions that power next-generation consumer mobiles and adjacent markets—redefining possibilities at the frontier of technology development. You will define and deliver new SoC architecture and features for premium mobile and related product platforms. You excel at performance modeling and analysis for hardware features, developing tools and simulations to evaluate complex use cases—including gaming, camera, and ML workloads—and translating findings into innovative memory subsystem solutions. You ensure design excellence by assessing the impact of system-level architectural trade-offs across CPU, GPU, NPU, ISP, memory subsystems, and software, and delivering high-quality architectural proposal and specifications to design teams. You lead effective cross-functional collaboration with global teams, clearly communicating architecture proposals to diverse audiences—from peer engineers to leadership—while driving consensus, influencing data-driven decision making, and resolving challenges for efficient implementation of advanced memory technologies. You inspire high performance, mentor junior engineers, foster trust, and promote a culture of ownership culture and open communications.

Requirements

20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
Extensive experience in system-level architecture analysis and performance modeling, ranging from simple analytical models to complex cycle-accurate simulations and correlation, particularly across CPU – memory subsystems.
Knowledge of high performance, high efficiency design and design flow.
In-depth knowledge of existing and emerging JEDEC LPDDR memory standards.
In-depth knowledge of modern memory controller design including queue depth, scheduling, QoS, starvation, fairness, encryption, etc.
Strong proficiency in leveraging existing or developing new simulation capabilities.
Knowledge of on-device ML for LLMs.
Detailed knowledge of cache subsystems, including coherency, caching policies, and trade-offs of latency, bandwidth and hierarchies.
Strong communication and collaboration skills, with ability to navigate and guide others through ambiguity in a fast-paced, global team environment.

Nice To Haves

Knowledge of HBM and DDR.
Understanding of CPU/GPU/NPU ML acceleration.
Familiarity with processing in memory (PIM).
Knowledge of in Interconnect and bus protocols, with CHI/ACE interconnect experience.
Experience with the Android Ecosystem and analysis tools.
Experience with Arm Architecture and ecosystem.

Responsibilities

Define and drive the architecture of SoC memory and cache subsystems for Samsung’s premium chipsets, with a strong focus on enabling on-device machine learning.
Identify and analyze emerging use cases, propose innovative memory architectures, and experiment with new ideas in collaboration with global cross-functional teams.
Define and deliver new SoC architecture and features for premium mobile and related product platforms.
Excel at performance modeling and analysis for hardware features, developing tools and simulations to evaluate complex use cases—including gaming, camera, and ML workloads—and translating findings into innovative memory subsystem solutions.
Ensure design excellence by assessing the impact of system-level architectural trade-offs across CPU, GPU, NPU, ISP, memory subsystems, and software, and delivering high-quality architectural proposal and specifications to design teams.
Lead effective cross-functional collaboration with global teams, clearly communicating architecture proposals to diverse audiences—from peer engineers to leadership—while driving consensus, influencing data-driven decision making, and resolving challenges for efficient implementation of advanced memory technologies.
Inspire high performance, mentor junior engineers, foster trust, and promote a culture of ownership culture and open communications.