SoC Architect (Coherent Interconnect)

Samsung•San Jose, CA

7d•$180,200 - $297,200

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities We’re seeking a highly experienced and skilled SoC Architect to lead the design and development of coherent interconnect architectures for next-generation System-on-Chip (SoC) products. As a key member of our SoC Architecture team, you will be responsible for defining and implementing innovative, high-performance, and low-power interconnect solutions that enable seamless communication between various IP blocks and subsystems within our SoCs. You provide technical leadership and expertise in the design and development of coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g., AXI, ACE, CHI etc.). You collaborate with cross-functional teams to define and optimize SoC architectures, ensuring that interconnect designs meet system performance, power, and area requirements. You lead the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics. You analyze and optimize interconnect performance, power consumption, and area efficiency using simulation tools, modeling, and benchmarking. You work closely with various stakeholders, including system architects, IP designers, and software teams to ensure seamless integration of interconnect IP into SoC designs. You contribute to the development of technical roadmaps for coherent interconnect architectures, aligned with Samsung's strategic goals and industry trends. You mentor junior engineers and share knowledge and expertise with the team to ensure skill growth and expertise development. The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance- and power-optimized IP solutions that support advanced system modeling and real-world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments. Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next-generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth.

Requirements

15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD.
Extensive background in designing and developing SoC architectures, specializing in coherent interconnect design and related technologies
Proficiency NoC architectures and protocols, including AXI, ACE, CHI, and other industry-standard interfaces
Expertise in cache coherence protocols (e.g., MESI, MOESI, etc.)
Skilled in designing interconnect IP to enable efficient data transfer and communication within SoCs
Experience with high-speed interface protocols such as PCIe, USB, and other standardized interfaces
Strong understanding of system-level design principles and optimization techniques
Proficiency in programming languages such as C, C++, Python, and Verilog/VHDL
Proven experience in technical leadership, collaboration, and communication with cross-functional teams

Responsibilities

Lead the design and development of coherent interconnect architectures for next-generation System-on-Chip (SoC) products.
Define and implement innovative, high-performance, and low-power interconnect solutions that enable seamless communication between various IP blocks and subsystems within our SoCs.
Provide technical leadership and expertise in the design and development of coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g., AXI, ACE, CHI etc.).
Collaborate with cross-functional teams to define and optimize SoC architectures, ensuring that interconnect designs meet system performance, power, and area requirements.
Lead the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics.
Analyze and optimize interconnect performance, power consumption, and area efficiency using simulation tools, modeling, and benchmarking.
Work closely with various stakeholders, including system architects, IP designers, and software teams to ensure seamless integration of interconnect IP into SoC designs.
Contribute to the development of technical roadmaps for coherent interconnect architectures, aligned with Samsung's strategic goals and industry trends.
Mentor junior engineers and share knowledge and expertise with the team to ensure skill growth and expertise development.