Interconnect System Architect

Microsoft•Redmond, WA

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Hardware Systems Engineering (CHSE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an Interconnect System Architect to join the System Design team. The Interconnect System Architect drives co-design efforts between silicon and system teams, integrating cutting-edge interconnect technologies. This role is pivotal for next-generation high-speed connectivity solutions across Microsoft hardware platforms. The ideal candidate will have demonstrated significant experience in high speed system design with advanced interconnectivity technologies. Our team is at the forefront of technology and system design, leading the way for the next generation of platforms. Our mission is to architect the most performant, secure, reliable, and cost-effective solutions that are deployed at hyperscale to power Azure. The architect filling this role will be the subject matter expert to address the interconnectivity challenge in the silicon package, in the module, in the tray, in the rack and in the cluster. The architect will collaborate with the Planning and Sourcing teams and with Mechanical and Thermal Architects on requirements capture, technology insertion, concept proposals, cost/performance tradeoffs, prototype engineering, and architectural documentation for design/planning reviews. Once a program is approved from a conceptual level, the Architect will partner with the development teams to ensure a smooth transition to full product development. This individual will also champion innovative technical principles, design strategy and forward-looking technologies related to industry trends, drive the codesign with the full hardware stack from silicon to node, rack and cluster. Helping articulate and define our next generation interconnectivity technology. Come join this exciting and growing team through our monumental evolution of cloud hardware at Azure and Microsoft!

Requirements

Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 9+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 11+ years technical engineering experience
OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Nice To Haves

BS/MS in Electrical Engineering, Computer Engineering, or related field.
15+ years in interconnect/system architecture, SI/PI, and high‑speed link design for large‑scale systems (servers, accelerators, networking, or comparable).
Proven silicon–package–board co‑design experience: channel definition, PHY requirements, equalization/FFE/DFE tradeoffs, retimer/redriver choices, and end‑to‑end closure.
Hands‑on modeling & simulation (e.g., IBIS‑AMI/Statistical/Time‑Domain, S‑parameter manipulation, eye/jitter analysis) and relevant EDA/EM tools (e.g., HFSS, Clarity/Siemens/Ansys, ADS, Sigrity, HSPICE/PrimeSim, MATLAB/Python).
Demonstrated cross‑functional leadership and communication skills—able to drive architecture decisions and tradeoffs with senior technical leaders.
Proven analytical and problem-solving skills with a focus on performance optimization.
Proven intellectual curiosity and a passion for challenging the status quo and driving disruptive innovation
PhD in EE/CE/Physics (or equivalent).
Expertise with PCIe Gen6/Gen7 (PAM4), Ethernet 112G/224G PAM4, UCIe/XSR/USR links, retimer/redriver, CPC and CPO considerations.
Experience with advanced packaging (2.5D/3D, HBM, organic/ABF, glass/interposers), substrate design rules, and warpage/thermo‑mechanical interactions.
System‑level architecture across node/rack/cluster, including thermal‑mechanical constraints, serviceability, and manufacturability at cloud scale.
Track record of public technical contributions (e.g., DesignCon/Hot Interconnects/OFCS papers, standards proposals), patents, or open‑source/consortia leadership.
Deep insight in global supply chain dynamics and technology trends

Responsibilities

Lead silicon–system co‑design for high‑speed electrical and optical interconnects (die‑to‑die, package, board, cable/backplane), ensuring coherent requirements flow between SoC/ASIC, packaging, module, and system architectures.
Drive the interconnect technology roadmap, define inflection points, readiness criteria, and insertion plans across near‑, mid‑, and long‑term horizons; drive make/buy/partner decisions with clear TCO, risk, and schedule tradeoffs.
Drive end‑to‑end SI/PI performance, spanning package→module→tray→rack→cluster to deliver scalable bandwidth density, latency, power, and reliability targets. Work with SI team to establish channel budgets; guide stack‑ups, materials, connector/cable selections; standardize modeling, simulation, and validation methodologies for BER/jitter, crosstalk, S‑parameters, and compliance.
Represent Microsoft at industry conferences/consortia and in standards efforts (OIF, IEEE, OCP, OFC, etc.), publish/present to advance ecosystem alignment.
Influence roadmaps with PHY, connector, substrate, PCB, cable, and optical vendors; evaluate emerging technologies; incubate POCs that de‑risk insertion into program plans.

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