Senior HSIO Digital Design Engineer
About The Position
Samsung’s San Jose Location Group in US was established in October 2012 to develop industry leading location technology IP for mobile and wearable applications. The group develops premium tier products and drives the technology for next generation products. The team is responsible for all aspects of building products from concept (algorithm design) to productization – i.e., architecture definition, silicon design, algorithm and software development, platform integration, performance optimization, test and commercialization. The Location Group is an integral part of the broader SoC organization responsible for Exynos line of SoC products that cover all IPs including Application Processor, Communication Processor, Connectivity, GPU, NPU etc. and hence enables us to develop highly integrated products and optimize our solution to be the best in class. This team is focused on next-generation HSIO (High-Speed I/O) design for Samsung’s AI production platforms. Ideal candidates will have 3+ years of industry experience specializing in digital design for die-to-die(chiplet) interfaces or similar high-speed I/O technologies. Candidates are expected to have a strong understanding of the end-to-end digital design flow and the ability to collaborate effectively with system and analog teams.
Requirements
- 3+ years of industry experience specializing in digital design for die-to-die(chiplet) interfaces or similar high-speed I/O technologies
- Strong understanding of the end-to-end digital design flow
- Ability to collaborate effectively with system and analog teams
Nice To Haves
- Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link
- Familiarity with HSIO PHY layers protocols and architectures
Responsibilities
- BS in Electrical Engineering with 5+ Years of experience, MS in Electrical Engineering with 3+ years of experience or PhD in Electrical Engineering
- Hands-on experience in High-Speed I/O PHY IP development, with expertise in one or more of the following areas:
- Strong understanding of high-speed serial interconnect protocols and associated design trade-offs
- Solid understanding of how analog and mixed-signal design and verification impact digital-on-top development flows
- Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs
Benefits
- Medical/Dental/Vision/401k
- Charitable giving match
- 4+ weeks of paid time off a year, plus holidays and sick leave
- Stipend for fertility care or adoption
- Medical travel support
- Virtual vet care
- On-demand apps and free confidential therapy sessions
- Onsite Café and gym, plus virtual classes
- Flexible environment
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What This Job Offers
Job Type
Full-time
Career Level
Senior
