Senior High-Speed PCB Engineer - TeraWave

BLUE ORIGIN•Seattle, WA

7d•$156,802 - $219,522

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in high-speed PCB design and hardware development in a product development environment.
Demonstrated track record of designing and shipping complex, high-speed multi-layer PCBs from concept through high volume production.
Deep expertise in signal integrity analysis, including pre/post-layout SI simulation, eye diagram analysis, crosstalk characterization, and physical layer correlation measurements.
Hands-on experience with advanced PCB manufacturing technologies.
Proven experience designing high speed memory interfaces.
Hands-on experience designing PCB layouts for serializers and deserializers (SerDes) at data rates of 10 Gbps and above.
Experience designing microprocessor and SoC PCB implementations.
Strong expertise in power integrity (PI) design and verification, including PDN target impedance analysis, decoupling network simulation, and physical PDN impedance measurement and validation.
Experience with PCB design for manufacturability (DFM) and design for testability (DFT).
Excellent technical documentation and communication skills.
Background in production hardware including supply chain coordination, PCB fabrication vendor management, assembly oversight, and yield optimization for high-reliability assemblies.

Nice To Haves

Master's degree in Electrical or Computer Engineering.
10+ years of relevant high-speed PCB design experience.
Experience designing electronics for thermal conduction environments (no convective cooling), as required for space-deployed hardware — including thermal heat sink design, and component placement.
Experience with radiation effects on electronics (SEE, TID, displacement damage) and associated PCB-level and component-level mitigation techniques for the target orbital environment. This includes redundancy where necessary to meet mission reliability requirements.
Hands-on environmental qualification testing experience (Thermal vacuum - TVAC, vibration, EMI/EMC) correlated to PCB design decisions.

Responsibilities

Lead the physical design of complex, multi-layer PCBs for the TeraWave network switch platform.
Perform pre- and post-layout signal integrity (SI) analysis, including SerDes lanes, DDR memory buses, and high-density Ethernet switch interconnects.
Apply advanced PCB design techniques including: Controlled impedance routing for differential pairs and single-ended high-speed signals. Via structures to minimize stub lengths and optimize signal path routing in high-density designs. Dielectric material — understanding how material affects differential pair skew and impedance variation and applying strategies.
Define and review PCB layer stack-ups in collaboration with PCB fabricators, specifying laminate materials, prepreg selection, copper weights, and via structures to meet SI, power integrity, and manufacturing reliability and yield requirements including coupon testing.
Develop and execute full 3D electromagnetic (EM) simulation models of critical PCB structures extracting broadband S-parameter models that capture frequency-dependent losses, reflections, and crosstalk without reliance on simplified lumped element approximations.
Perform SI simulation to validate eye margins, crosstalk levels, and model accuracy versus physical measurement.
Apply de-embedding techniques and use VNA measurements and TDR analysis to correlate simulated SI results with physical hardware measurements.
Design DDR4, and/or DDR5 memory subsystems with a thorough understanding of fly-by topology, write leveling, read/write training, and the constraints imposed by the memory controller.
Understand and account for the PCB routing limitations of processor and microcontroller memory interfaces, including: Byte lane grouping and skew budgets within and across DQ groups. Address/command bus fly-by routing and stub minimization. Reference plane continuity and return current management beneath DDR routing fields. PCB trace length matching requirements relative to clock and strobe signals.
Demonstrate DDR compliance through laboratory measurements.
Design PCB layouts for high-speed serializer/deserializer (SerDes) interfaces including 10GbE, 25GbE, 40GbE, 100GbE, and beyond.
Experience in PCB design implementations for microprocessors and SoCs (ARM, RISC-V, MPSoC, or equivalent), understanding the physical routing constraints and signal integrity limitations of high pin-count BGA packages including escape routing, via-in-pad usage, and power delivery network design beneath the device.
Optimize high-speed connector and backplane interfaces for minimum via stub and maximum channel insertion loss margin.
Architect and design low-impedance power delivery networks (PDNs) for high-current, noise-sensitive devices including switch ASICs, microprocessors, FPGAs, and DDR memory, with target impedance profiles defined across the full frequency range of interest.
Perform PDN simulation using frequency-domain tools to verify decoupling capacitor placement, value selection, and plane resonance suppression.
Execute power integrity (PI) measurements including VNA-based PDN impedance measurements, time-domain load transient validation, and switching noise characterization to verify simulated PDN performance against physical hardware.
Design multi-stage LC filtering and high-PSRR LDO post-regulation stages to isolate sensitive analog and high-speed digital supply rails from switching converter noise.
Apply plane-splitting, via stitching, and decoupling placement strategies to prevent power-plane noise coupling into high-speed signal paths.
Apply rigorous DFM practices throughout the PCB design process, including: Via and pad structure selection compatible with the PCB fabricator's manufacturing capabilities (microvia aspect ratios, back-drill depth tolerances, controlled-depth routing). Copper feature sizing, annular ring, and clearance rules consistent with the target fabrication class (IPC Class 2/3 as appropriate for space hardware). Component placement and routing strategies that support automated optical inspection (AOI), X-ray inspection, and solder paste printing yield.
Implement comprehensive DFT strategies including: Boundary scan (JTAG) chain architecture across the board for structural test coverage. Dedicated test point placement for in-circuit test (ICT) and flying probe access to critical nets. Built-in self-test (BIST) hooks at the PCB level in collaboration with firmware teams. Test connector and loopback provisions for high-speed interface validation during board bring-up and manufacturing test.
Work closely with PCB fabricators and contract manufacturers during design review cycles to validate manufacturing feasibility before release to fabrication.
Demonstrate compliance through laboratory measurements.
Demonstrate working knowledge of electromagnetic compatibility (EMC) design principles encompassing all four fundamental compliance categories: conducted emissions, radiated emissions, conducted susceptibility, and radiated susceptibility.
Apply this understanding at the PCB design level through deliberate implementation of mitigation strategies including: strategic placement and selection of filter components on power entry and signal interface lines; chassis ground stitching via placement and guard trace strategies; shielding; and bulk decoupling and filtering power inputs designed to suppress conducted noise.
Demonstrate compliance through laboratory measurements.
Lead hardware bring-up and validation of the TeraWave switch PCB, including power sequencing, high-speed interface eye diagram characterization, BER testing, individual component compliance through environmental testing.
Develop and execute hardware validation test plans covering SI/PI measurements, functional test, and environmental screening as appropriate.
Support resolution of complex PCB-related hardware issues identified during bring-up, integrating root cause findings back into PCB design guidelines and DFM/DFT standards.
Collaborate with firmware and software teams on BSP integration, device driver bring-up, and hardware-software interface debug for network switch and embedded management subsystems.