Senior Hardware Test Engineer– System on Chip

GM•Warren, MI

9d•Hybrid

About The Position

General Motors is at the forefront of the transformation of automotive with the electrification of our portfolio and the development of leading-edge central compute, connectivity, and autonomous capabilities. Our Semiconductor Engineering team is a dynamic, high‑energy, and innovative group focused on design and commercialization of leading‑edge silicon enabling the future of GM’s Software Defined Vehicle (SDV) platforms – central compute units, connectivity modules, and other controllers. We are seeking a highly skilled and driven Senior Hardware Test Engineer to join our Semiconductor Center of Excellence. This pivotal role will lead the definition, development, and execution of hardware test strategies for state‑of‑the‑art System‑on‑Chip (SoC) solutions used in next‑generation automotive electronics platforms. You will be responsible for SoC and SoC‑centric ECU board bring‑up, test plan creation, automated test development, and systematic debug to ensure our silicon and hardware platforms meet functional, performance, and reliability goals from early samples through production.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or a related field.
7+ years of experience in hardware validation or test engineering for complex digital systems, SoCs, or high‑integration ECUs.
Strong understanding of SoC subsystems and IP blocks (CPU, GPU/NPU, memory controllers, high‑speed I/O, power management, and peripherals) from a validation and debug perspective.
Proven hands‑on experience bringing up and testing complex digital boards, including power sequencing, clock/reset validation, and interface bring‑up.
Demonstrated experience creating and executing structured hardware test plans, including definition of objectives, coverage, pass/fail criteria, and traceability to requirements.
Proficiency with lab equipment such as oscilloscopes, logic analyzers, protocol analyzers, power supplies, electronic loads, and precision power / current measurement tools.
Hands-on experience with SoC and/or board-level electrical characterization (for example voltage/current limits, static and dynamic power, leakage, timing margins, and I/O thresholds) across PVT corners, including correlation to specifications and models.
Practical experience debugging high‑speed interfaces (for example DDR, PCIe, Ethernet, MIPI, or similar), including interpretation of signal integrity and timing issues.
Strong analytical and problem‑solving skills, with the ability to isolate root causes across silicon, board, and software boundaries.
Exceptional collaboration and teamwork skills; proven ability to work across functional and organizational boundaries.
Demonstrated ability to manage multiple test efforts in parallel, including planning, execution, and reporting.

Nice To Haves

Master’s degree in electrical engineering, computer engineering, or a related field.
Experience developing automated hardware tests and data collection scripts (for example Python, C/C++, or similar scripting environments).
Experience with validation of automotive or other safety‑critical SoCs and ECUs.
Experience defining and executing environmental, reliability, and margin testing (for example voltage/temperature corners, jitter and eye diagrams, long‑duration stress).
Experience with test automation frameworks, CI pipelines, and lab management tools used to run large‑scale automated regressions.

Responsibilities

Define end-to-end hardware test strategies and structured bring-up plans for SoCs and associated components (memory, power) across EVKs, reference boards, and ECUs, including power-on sequencing, clock/reset validation, basic sanity, interface bring-up, regression suites, coverage goals, and clear pass/fail criteria.
Plan and execute SoC and board-level electrical characterization testing (for example voltage/current limits, static and dynamic power, leakage, timing margins, and I/O thresholds) across PVT corners and operating modes.
Design, implement, and maintain automated test frameworks and scripts (for example, Python, C/C++, or similar) to improve coverage, repeatability, and execution efficiency.
Develop test content and automation for key SoC subsystems and interfaces, such as DDR, PCIe, Ethernet, MIPI, USB, and high‑speed SerDes, including margin and stress testing.
Use lab equipment (oscilloscopes, logic analyzers, protocol analyzers, power supplies, electronic loads, JTAG tools, etc.) to characterize signals, validate timing and margins, and root‑cause hardware issues.
Partner closely with SoC hardware design engineers, ECU hardware teams, and software teams to translate system requirements into concrete test cases and coverage metrics.
Develop and maintain reusable test procedures, documentation, and checklists that can be applied across multiple programs and platforms.
Support DV/PV and component environmental testing by defining hardware functional monitoring, lab setups, and diagnostics required to exercise SoC‑level functionality.
Provide technical mentorship and guidance to junior engineers on test methods, lab best practices, and debug techniques.