Senior Hardware (FPGA) Engineer

LMI Technologies•Burnaby, BC

21h•Hybrid

About The Position

LMI is seeking a talented Senior Hardware (FPGA) engineer to join a multi-disciplinary engineering team. The successful candidate will have a proven record in developing complex FPGA code for an embedded environment. The candidate will be responsible for FPGA designs for a distributed system which includes machine vision, cameras, laser drivers, high speed communication channels and image processing. The candidate will be involved in the complete FPGA development cycle, from design to simulation, release and support.

Requirements

Bachelor Degree in Electrical Engineering
Minimum 5+ years relevant experience designing and testing digital logic (FPGA or ASIC)
Hands-on experience designing with VHDL and/or Verilog complex systems with multiple clock-domains, high speed interfaces (LVDS, PCIe, memories, MIPI, MGT) and data processing cores is required.
Hands-on experience with self-verifying simulation environments and techniques
Strong ability in tracking and identifying FPGA problems (logic, timing, implementation, synchronization)
Experience with HW debugging tools (logic analyzers, Chipscope)
Experience in translating high level requirements into an architecture, considering aspects like resource/power use, performance, ease of maintenance, compatibility and design partitioning into modules or hardware and SW functions.
Able to produce solid designs in a fast-paced environment
Passionate for leading edge technology, out of the box thinking and its challenges
Capable of working in small teams and be accountable for your performance and documentation

Nice To Haves

Xilinx’ Zynq7K and MP, AXI interfaces, Xilinx IP, Vivado, Xilinx ISE, and Chipscope for FPGA development
FPGA/SoCs from other vendors (Intel, Lattice)
Image processing and machine vision concepts
AI concepts and coding tools (Claude, Gemini)
Designs incorporating soft core CPUs: Microblaze, Picoblaze
Higher level design languages (System Verilog, System C) and tools or flows (i.e. Vivado HDL)
Verification (UVM)
Other languages: TCL, C/C++
Experience with Oscilloscopes and Logic Analyzers for development and debugging
P.Eng designation or working towards it would be desirable

Responsibilities

Lead the design and implementation of high-performance RTL using VHDL, Verilog and SystemVerilog
Define FPGA architecture and micro-architecture specifications based on system-level requirements
Collaborate with other teams in the technology department to define HW/SW interfaces and memory maps.
Select appropriate FPGA vendors (Xilinx/AMD, Intel, Microchip) and specific chip families based on project needs.
Design and maintain self-checking testbenches using SystemVerilog/UVM or VHDL/OSVVM to ensure high functional coverage.
Implement constrained random stimulus generation to uncover complex corner cases that manual directed tests might miss.
Deeply analyze data sheets from FPGA vendors and external component providers (ADCs, DACs, PHYs) to verify timing, voltage, and power compatibility.
Mentor other engineers through code reviews and technical guidance.
Conduct feasibility studies for new features or hardware platforms.
Interface with vendors to resolve tool-specific bugs or procure IP cores.

Benefits

Full health care coverage (with 100% paid premiums) including dental, vision, and drugs for you and your family.
Hybrid work arrangements
Flextime
Competitive paid time off
An annual Education Support Program for training and professional growth
Annual performance reviews
Free snacks and drinks
Team-building events
Tenure awards
Official "May the 4th" (Star Wars Day) company holiday!
Access to an on-site fitness facility
Access to tennis/basketball court
Company-wide wellness initiatives
Eligibility for Profit Sharing Program Participation