Senior Hardware Circuit Design Engineer (Memory Test, Teradyne, Tualatin, OR)

Teradyne•Tualatin, OR

12d•$145,600 - $233,000

About The Position

As a Hardware Circuit Design Engineer, you will be responsible for concept-through-production design of analog and mixed-signal instruments for automated test equipment. The role involves complex activities related to designing new products, investigating customer-reported problems to identify root causes, and implementing improvements in design, testing, and operations. The position is based in Tualatin, Oregon, and is not eligible for visa sponsorship.

Requirements

10 or more years of experience as a circuit design engineer.
Experience designing digital and analog board-level circuitry.
Expertise in op-amp-based circuitry, signal conditioning, filters, stability, compensation networks, and control loops.
Working familiarity with high-speed design techniques.
Expertise in switching power supply design and related noise and crosstalk issues on multilayer PCBs, including measurement techniques.
Experience with high-power signal delivery methods.
Knowledge of thermal and mechanical fundamentals.
Relevant PCB layout experience to guide CAD personnel.
Experience with circuit simulation tools such as SPICE, ADS, or Ansys.
Strong communication skills and ability to work with geographically dispersed multifunctional teams.
Desire to take on project ownership.
Proven ability to inspire junior engineers.
Self-starter.
Desire to work as a team with a results-driven approach.
Strong problem-solving and reasoning skills.
BSEE, MSEE, or equivalent.

Responsibilities

Design analog and mixed-signal instruments for automated test equipment from concept through production.
Design digital and analog board-level circuitry.
Investigate customer-reported problems and evaluate root causes.
Implement improvements in design, testing, and operations.
Guide CAD personnel on PCB layout.
Take ownership of projects.
Work with geographically dispersed multifunctional teams.
Inspire junior engineers.