Senior Full Chip Physical Design Integration Lead

Intel Corporation•Worcester, MA

1d•$164,470 - $311,890•Hybrid

About The Position

Join Intel as SOC Physical Design Engineer, where you will play a pivotal role in shaping the future of custom IP and SoC designs. In this position, you will drive the physical design implementation of cutting-edge technologies, transforming RTL to GDS databases ready for manufacturing. Your expertise in physical design flows will directly contribute to optimizing power, frequency, and area metrics, enabling Intel to deliver high-performance products that empower innovation worldwide. This is an opportunity to be part of a dynamic team where your work will have a meaningful impact on Intel's mission to push the boundaries of technology and deliver industry-leading solutions.

Requirements

Bachelor's degree with 8+ years or master’s degree with 6+ years or PhD. with 4+ years in Electrical/ Electronic Engineering, Computer Engineering, Computer Science or a related technical discipline.
4+ years of experience with the following technical skills: Proficiency in physical design flows, including synthesis, place and route, clock tree synthesis, and static timing analysis.
Expertise in design optimization for physical design, multi-power plane design (MPP/UPF), and RTL to GDS workflows.
Hands-on experience with scripting to automate design flows.
Knowledge of EDA tools and methodologies for verification, reliability, timing closure, and power integrity analysis.

Nice To Haves

Expertise in Design planning, Hierarchical design, SOC floorplan and optimizations.
Strong analytical skills with the ability to identify and resolve complex design challenges efficiently.
Effective communication skills and the ability to work collaboratively within a team-oriented environment.
Experience developing and improving physical design methodologies and automation tools.
Familiarity with industry trends and emerging technologies in physical design, ensuring designs remain forward-thinking and innovative.

Responsibilities

Work on SOC floorplan, Pin and macro placement optimizing area and efficiency.
Perform physical design implementation for custom IP and SoC designs across the entire design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
Conduct verification and signoff activities such as formal equivalence verification, reliability verification, power integrity analysis, and layout verification using industry-standard EDA tools.
Drive design optimization across multiple power domains, static and dynamic power integrity analysis, and structural design checking.
Participate in the development and enhancement of physical design methodologies and flow automation.
Collaborate with cross-functional teams to ensure designs meet product-level parameters, quality benchmarks, and are ready for manufacturing.