Senior FPGA Verification Engineer

Anduril Industries • Costa Mesa, CA

21h • $146,000 - $194,000 • Onsite

About The Position

We are looking for a Senior FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA. You will lead verification strategy and methodology for FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, owning UVM-based methodology, coverage-driven verification, and the roadmap for verification tooling across our programs. You will set technical direction for the verification team and mentor other engineers while partnering closely with design, systems, and program leadership. If you have led verification closure on production avionics or flight programs and want to shape how a growing team works, this role is for you.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• 7+ years of experience in FPGA/ASIC verification
• Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
• Object-oriented programming principles
• Industry simulators (Questa, VCS, Xcelium, or Vivado)
• Git-based collaborative workflows including code review
• Linux development environments
• SVUnit or equivalent unit-testing frameworks
• Formal verification or CDC verification tools
• Verification automation scripting (Python, Tcl, Makefile)
• Track record owning verification closure on a production or flight program end-to-end
• Experience defining verification methodology and mentoring engineers
• Strong communication and teamwork skills
• Eligible to obtain and hold a U.S. Secret security clearance

Nice To Haves

• 10+ years of experience in FPGA/ASIC verification
• Master’s degree in Electrical Engineering, Computer Engineering, or related field
• DO-254, avionics verification standards for UAS, and safety-critical verification processes
• Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI
• SoC and ARM-based embedded platforms
• Verification automation, CI/CD integration, and Nix-based build environments
• UVM base-class and framework library development
• DO-254 DAL A/B artifact ownership and experience supporting DER or customer audits

Responsibilities

• Define UVM architecture and reusable verification component libraries used across programs
• Mentor verification engineers by reviewing testbenches, verification plans, and coverage models
• Represent verification in design reviews and program milestones
• Drive verification tooling, CI/CD, and regression infrastructure roadmap for the team
• Architect UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs and establish patterns others on the team follow
• Develop verification plans with traceability to system and hardware requirements
• Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
• Build functional coverage models and drive code coverage analysis to closure
• Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs
• Establish and maintain regression suites, tracking coverage metrics and verification progress
• Debug failures using waveform tools and simulation logs at the HDL and system level
• Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement
• Support hardware validation and board bring-up on target platforms
• Ensure verification meets DO-254 and relevant safety standards
• Author verification closure reports and coverage analysis summaries

Benefits

• Comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next.
• Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior