Senior FPGA Engineer
About The Position
Akuna Capital is an innovative trading firm with a strong focus on collaboration, cutting-edge technology, data driven solutions, and automation. We specialize in providing liquidity as an options market-maker – meaning we are committed to providing competitive quotes that we are willing to both buy and sell. To do this successfully, we design and implement our own low latency technologies, trading strategies, and mathematical models. Our Founding Partners first conceptualized Akuna in their hometown of Sydney. They opened the firm’s first office in 2011 in the heart of the derivatives industry and the options capital of the world – Chicago. Today, Akuna is proud to operate from additional offices in Sydney, Shanghai, London, and Singapore. We are looking for Senior FPGA Engineers to accelerate various portions of our trading platform. Members of the Hardware Development team will work with cutting-edge FPGA technology and high-performance computing architectures – owning projects end-to-end and making Akuna’s systems faster and smarter.
Requirements
- 10+ years of experience in FPGA or ASIC digital logic design – network traffic experience a strong plus
- Deep Verilog/SystemVerilog or VHDL skills
- Solid grasp of static timing analysis, synthesis, and place-and-route tools
- Familiarity with algorithms, data structures, and verification/unit testing workflows
- Python and Bash scripting fluency
- Enthusiasm for collaboration with other FPGA team members as well as members from software and trading teams
- Open mindedness for novel development approaches and architectures
- The ability to react quickly and accurately to rapidly changing market conditions, including the ability to quickly and accurately respond and/or solve math and coding problems are essential functions of the role
Responsibilities
- Own projects - driving project progression from inception, requirements, architecture, design entry, timing closure and verification
- Partner closely with the Low Latency, Trading and other teams to foster and develop ideas that performance
- Develop and maintain RTL in Verilog/SystemVerilog
- Write and maintain verification environments
- Design optimization for timing closure
- Develop and maintain project documentation
Benefits
- employer-paid medical, dental, vision
- retirement contributions
- paid time off
- discretionary performance bonus
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
