Senior FPGA Engineer

Tangram Flex • Dayton, OH

1d • Hybrid

About The Position

Tangram Flex is seeking a Senior FPGA Engineer with a Software/Firmware Focus will design, develop, and optimize high-performance digital logic circuits. This role bridges the gap between hardware architecture and low-level software. The engineer is responsible for implementing complex digital signal processing (DSP) algorithms, managing high-speed data protocols, and ensuring seamless integration with host software systems. Our team and products provide solutions to enable innovators to design, develop, verify, and advance critical systems, while accelerating innovation that advances our nations’ security. By accelerating delivery of critical systems, Tangram is transforming the way our nation solves complex software challenges.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Science or a related field
• Ability to obtain or possess a current/or recent U.S. Government Security (DoD) Clearance. U.S. citizenship is required to obtain clearance
• Proficiency in VHDL, Verilog, or System Verilog.
• Strong programming skills in C, C++, and scripting languages like Python or Tcl for automation.
• Mastery of vendor tools such as AMD/Xilinx Vivado, Intel Quartus, or Microchip Libero.
• Experience with High-Level Synthesis (HLS), Digital Signal Processing (DSP), and SoC architectures (e.g., ARM-Cortex embedded in FPGA).
• Deep understanding of high-speed interfaces like PCIe, Ethernet (10G/100G), DDR4/DDR5, and AXI streaming.

Nice To Haves

• 5+ years of hands-on experience in FPGA design and embedded software development.
• Industry-specific experience in areas like RF/SDR, defense, automotive (ADAS), high-frequency trading, or data centers.

Responsibilities

• Translate complex software requirements into optimized Register Transfer Level (RTL) architecture.
• Design, implement, and test custom intellectual property (IP) blocks using VHDL, Verilog, or SystemVerilog.
• Develop low-level C/C++ drivers, Linux kernel modules, and APIs to connect FPGA logic with embedded microprocessors.
• Write comprehensive testbenches (using UVM or SystemVerilog) and utilize hardware-in-the-loop (HIL) testing with oscilloscopes and logic analyzers.
• Analyze and optimize logic placement, routing, and clock domains to meet strict hardware timing and power constraints.

Benefits

• Hybrid work options
• Flexible Working Hours
• 10 paid holidays
• generous Paid Time Off
• Employer Paid Medical, Dental, Vision and Short and Long Term Disability Insurance
• Access to group rating plans for Life Insurance
• Employer contribution to Health Savings Account
• Competitive 401K employer match

What This Job Offers

• Job Type: Full-time
• Career Level: Senior