Senior FPGA Engineer

SEAKR Engineering • Greenwood Village, CO

22h • $130,000 - $185,000

About The Position

Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space. Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs. Candidate shall have experience with completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity. Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs. FPGA technology differences (Xilinx vs Actel/Microsemi). FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero. Scripting languages such as TCL or Python. Leading small sized teams in order to develop moderately complex systems according to program schedule expectations.

Requirements

• Extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs
• FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design
• Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers
• Clear written and verbal communication skills

Nice To Haves

• Knowledge of RTL design techniques for radiation upset mitigation
• Experience using multiple RTL languages

Responsibilities

• Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity
• Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs
• FPGA technology differences (Xilinx vs Actel/Microsemi)
• FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero
• Scripting languages such as TCL or Python
• Leading small sized teams in order to develop moderately complex systems according to program schedule expectations
• Provide support and technical direction to junior engineers

Benefits

• Medical insurance
• Dental insurance
• Vision insurance
• 401(k) retirement plan
• Year-end bonus
• Vacation
• Sick leave
• Bereavement leave
• FMLA leave

What This Job Offers

• Job Type: Full-time
• Career Level: Senior