Senior FPGA Design Engineer

RTX • Tucson, AZ

3d • $86,800 - $165,200 • Onsite

About The Position

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and Microsemi. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.

Requirements

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience
• Experience with at least one of the following: FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using SystemVerilog coding
• Working with Xilinx or Microsemi devices and associated flow tools
• Delivering FPGA/ASIC solutions for system-level applications
• Active and transferable U.S. government issued security clearance is required prior to start date.
• U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
• Ability to obtain INTERIM U.S. government issued security clearance is required prior to start date

Nice To Haves

• FPGA/ASIC design experience in one or more of the following areas:
• Hands-on experience with integration and debugging of FPGA/ASIC devices
• Radar processing techniques
• Image processing techniques for visual and infrared sensors
• Embedded systems design using ARM, Microblaze, or Nios processors
• Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
• Constrained random verification in UVM using System Verilog
• Verification utilizing emulation platforms, such as Veloce

Responsibilities

• Design and deliver production quality FPGA releases from initial proof of concept up to production
• Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
• Translate system level requirements into FPGA requirements
• Design and code in VHDL for reliability and maintainability
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
• Help drive projects and execute program schedules on time and budget
• Create complete documentation including requirements, verification plan, and user’s guides
• Lead small teams and mentor junior engineers
• Support internal and external technical reviews

Benefits

• medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays
• annual short-term and/or long-term incentive compensation programs

What This Job Offers

• Job Type: Full-time
• Career Level: Senior