Senior Formal Verification Engineer - LPU

NVIDIA

2d•Hybrid

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Are you ready to be part of a team that is pushing the boundaries of AI and computing? At NVIDIA, we value innovation, collaboration, and excellence. Join our outstanding team as a Senior Formal Verification Engineer and be at the forefront of developing modern technology that builds the future. This role offers an outstanding opportunity to work with world-class talent and make a significant impact!

Requirements

BS/MS/PhD or equivalent experience in CS/CE/EE.
5+ years in ASIC verification with 3+ years passionate about formal verification methods.
Proficiency in SystemVerilog Assertions (SVA) and formal property verification.
Experience with at least one popular formal verification tool in the industry (JasperGold, VC Formal, etc.).
Excellent skills in applying AI tools in daily engineering work to efficiently solve problems.
Strong written and oral communication skills.
Keen attention to detail.

Nice To Haves

Demonstrated success in full-cycle formal sign-off for complex builds.
Expertise in formal applications: FPV apps, datapath verification, etc.
Deep understanding of GPU or LPU architecture build.

Responsibilities

Verifying AI-related sophisticated ASIC builds & features using advanced formal verification methods.
Collaborating closely with architecture and RTL teams to specify properties, resolve complex issues in building, and influence micro-architecture decisions.
Applying formal verification to rigorously ensure critical build properties align with specifications and minimize ambiguities.
Articulating formal verification coverage to partners.
Developing advanced formal verification environments and methodologies for complex ASIC designs, including building automated flows for scalability and efficiency.
Supporting silicon bring-up and debug using formal methods where applicable.