Senior Ethernet Performance Engineer

Cornelis Networks, Inc.•San Francisco, CA

5d•Remote

About The Position

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. We’re seeking a Senior Ethernet Performance Engineer to lead performance validation, debug, and characterization of our next-generation Ethernet-based networking silicon products—both internally and in customer environments. You’ll play a key role in post-silicon bring-up, lab-based performance validation, and collaboration with customers to optimize system performance. This is a high-impact, cross-functional role with visibility across silicon design, system architecture, software, and customer engineering teams.

Requirements

7+ years of experience in post-silicon validation, performance engineering, or silicon debug for networking or high-performance compute products.
Strong understanding of networking protocols and technologies (e.g., Ethernet, PCIe, switching, congestion control) , PFC, ECN, DCQCN .
Familiarity with data center performance requirements and benchmarks.
Scripting and automation skills (Python, Shell, etc.).
Excellent problem-solving and cross-functional communication skills.
Comfort working directly with customers, field engineers, and technical partners.

Nice To Haves

Deep understanding of networking and memory data flows, including technologies such as DPDK, RDMA, or similar high-performance I/O frameworks.
Background in silicon performance modeling, system architecture, or firmware/hardware co-design.
Exposure to cloud-scale workload analysis and performance tuning
Experience running HPC ( MPI application benchmarks) & AI (NCCL/RCCL benchmarks) .
Telemetry & Debugging: Investigating PFC deadlocks, packet drops, line-rate throughput, and tail latency using kernel tools, packet captures, and fabric telemetry.

Responsibilities

Building, configuring, and benchmarking Ethernet fabrics with RoCEv2 (RDMA over Converged Ethernet) to perform head-to-head performance evaluations against other network architectures (InfiniBand, Omni-Path, and rival Ethernet solutions).
Develop and execute validation and performance test plans targeting both internal lab and real-world data center deployment scenarios.
Analyze performance metrics such as throughput, latency, congestion, power efficiency, and architectural behavior under networking workloads.
Work directly with customers and field teams to reproduce, debug, and optimize performance issues in production environments.
Create diagnostic tools and scripts to collect, analyze, and visualize performance data.
Collaborate with architecture, firmware, and software teams to root-cause performance anomalies and recommend hardware or system-level improvements.
Translate validation and debug findings into actionable feedback for silicon and systems design.
Provide technical guidance and support to customers integrating and tuning our products in their data center infrastructures.