Senior Engineer (Multiple Openings)

Samsung•Austin, TX

1d•Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Requirements

Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering or in a closely related field plus two (2) years of experience in a related engineering occupation performing each of the following: Fusion compiler, Synopsys Primetime Tool Suite, TCL programming; data analysis using excel or JMP or any other equivalent tool; industry-standard timing signoff methodologies.

Responsibilities

Devise strategies and maximize product benefits in terms of Power, Performance, Area (PPA), Silicon Reliability, and design Turn-Around-Time (TAT).
Guide development of latest semiconductor technology nodes for optimized for GPU/CPU designs to meet product goals.
Explore and apply novel methodology for placement and routing to allow best power reduction for the designs.
Own all stages of block delivery starting from RTL clean-up, Synthesis, Placement, Clock tree generation, Routing and Physical verification.
Enable and use machine learning (ML) artificial intelligence tools to choose best standard cells and flow knobs and optimize them for the best solution.
Drive DTCO/TE (Design Technology Cooptimization/Technology Enablement) activities to improve PPA, Silicon Reliability, and design TAT.
Collaborate with cross-functional teams to unlock technology potential and achieve business success.
Perform Advanced Methodology development, ranging from Physical Design (P&R), transistor level/circuit Layout, Signoff, Electrical/Physical Verification up to DFM.
Coordinate with global design methodology teams and directly drive global R&D teams from various EDA vendors.