Senior Engineer, Physical Design Floorplan

Samsung Electronics • San Jose, CA

3d • Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Senior Physical Design Floorplan Engineer, you will play a key role in creating and optimizing top‑level floorplans that enable efficient physical‑design execution for SARC/ACL premium IPs. This highly visible position requires close collaboration with cross‑functional design teams, EDA partners, and intra‑functional groups. You will contribute strong problem‑solving skills and a deep understanding of floor‑planning challenges and best‑practice methodologies, ensuring robust, high‑performance, and low‑power implementations across Samsung’s premium mobile device tiers.

Requirements

• 5+ years of experience of professional experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 3+ years of experience with a Master’s degree, or 1+ years of experience with a PhD
• Skilled in EDA flows and methodologies and industry standards pertaining to Floor-planning
• Highly proficient in Top and Block level Floor-planning techniques including partitioning, pinning, and budgeting
• Experience with power-grid implementation and clock distribution
• Strong scripting and automation skills in Python, TCL, Shell, or Perl
• Hands on experience in delivering final GDS for high-performance IPs and SOCs

Nice To Haves

• Strong understanding of sign-off closure flows in deep-submicron technology in the domains of physical verification, STA, EMIR, and Power

Responsibilities

• You are a key contributor for the top‑level floorplan, driving block‑level floor‑planning and execution
• You execute and deliver key floor‑planning activities (placement, shaping, pinning, methodology) with production‑grade quality
• You drive the critical PPA aspects of floor‑planning by collaborating with the Architecture, RTL, PPA, and Physical Design teams
• You work with the CAD team to continuously improve the floor‑planning design methodology
• You lead the physical‑verification convergence of the top‑level floorplan to achieve final GDS delivery

Benefits

• medical
• dental
• vision
• life insurance
• 401(k)
• onsite lunch
• employee purchase program
• tuition assistance (after 6 months)
• paid time off
• student loan program
• wellness incentives

What This Job Offers

• Job Type: Full-time
• Career Level: Senior