Senior Engineer, GPU Front-End Integration

Samsung Electronics•San Jose, CA

3d•$139,000 - $208,400•Onsite

About The Position

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are building a center of excellence for Intellectual Property (IP) applied to high-performance computing devices. As a Senior GPU Front-End Integration Engineer, you will contribute to top-level RTL integration of complex GPU blocks and subsystems to deliver scalable, high-quality implementations for Samsung’s next-generation mobile GPUs. This mid-to-senior individual contributor role involves partnering closely with architecture, RTL, verification, and other design teams to resolve system-level challenges, support front-end integration strategy, and ensure execution readiness to meet market-competitive performance and power targets across concurrent GPU development cycles. The ideal candidate brings curiosity and knowledge in GPU/CPU RTL integration, front-end ASIC flows, and a collaborative mindset.

Requirements

2+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or a Master's degree.
2+ years of hands-on experience in GPU, CPU, or SoC RTL integration
Working understanding of front-end ASIC design flows, from RTL integration through synthesis and physical design handoff.
Proficient in RTL coding and integration using Verilog/SystemVerilog.
Working understanding of synthesis tools, timing analysis, floorplanning and PNR flow.
Good proficiency in scripting languages such as Python, Perl, Ruby, or TCL.
Excellent analytical and problem-solving skills.
Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
Excellent collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.

Nice To Haves

Understanding of ECOs and late-stage design changes.

Responsibilities

Contribute to the integration of complex GPU blocks and subsystems, supporting RTL partitioning decisions and integration strategies that ensure functional correctness, architectural alignment, scalability, and clean physical design across IP generations.
Drive front-end RTL quality and readiness by executing design quality checks—including lint, CDC, and logical equivalence—and delivering production-quality RTL to SoC and physical design teams.
Support RTL databases and manage memory macros, hard macros, and standard cell libraries, ensuring consistency, traceability, and integration robustness across projects.
Contribute to block-level synthesis, monitor area and timing metrics, and proactively identify integration risks related to performance, power, and implementation feasibility.
Take initiatives on moderate-to-complex projects and help advance best practices and methodologies by staying ahead of industry trends and emerging technologies.