Senior Embedded Software Engineer (C++) - Hardware Safety

Latitude AI • Detroit, MI

1d • Onsite

About The Position

Latitude AI develops automated driving technologies, including L3, for Ford vehicles at scale. We’re driven by the opportunity to reimagine what it’s like to drive and make travel safer, less stressful, and more enjoyable for everyone. When you join the Latitude team, you’ll work alongside leading experts across machine learning and robotics, cloud platforms, mapping, sensors and compute systems, test operations, systems and safety engineering – all dedicated to making a real, positive impact on the driving experience for millions of people. As a Ford Motor Company subsidiary, we operate independently to develop automated driving technology at the speed of a technology startup. Latitude is headquartered in Pittsburgh with engineering centers in Dearborn, Mich., and Palo Alto, Calif. Meet the team: The Embedded Software team develops foundational platform software critical to development across the company. The Hardware Safety & Power Systems group specializes in the real-time firmware that orchestrates safe system behavior during fault conditions, power transitions, and thermal events. We develop FreeRTOS and SafeRTOS-based drivers, state machines, and diagnostic frameworks for power management, thermal monitoring, voltage supervision, and hardware watchdog systems on TDA4 (Jacinto 7) embedded targets. Projects often require deep collaboration with hardware teams (PMIC vendors, SoC architects), safety engineers (ISO 26262 compliance), and system integration teams across the company.

Requirements

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, Robotics or a related field and 4+ years of relevant experience (or Master's degree and 2+ years of relevant experience, or PhD)
• Experience in embedded C/C++ with deep understanding of advanced language features, design paradigms, and embedded constraints (no exceptions, no RTTI, careful memory management).
• Proven ability to design clean abstractions and interface-based code for testability
• Proven expertise in ARM-based SoC architectures , specifically ARM Cortex-R5F: memory-mapped I/O, interrupt controllers (VIM), MPU configuration, cache behavior, and memory barriers.
• Experience debugging at the register level using datasheets
• Direct experience configuring MPUs and hardware-level firewalls to enforce spatial and temporal isolation in multi-core, safety-critical environments
• Experience building or significantly refactoring Hardware Abstraction Layers (HAL) to support multiple hardware targets, RTOS environments, or variant configurations. Understands the role of HAL in isolating driver complexity and enabling testing
• Ability to root-cause complex system failures — power sequencing hangs, missed watchdog feeds, thermal throttle race conditions, interrupt latency issues — involving shared memory, RTOS task scheduling, and hardware peripherals without supervision
• Ability to see potential pitfalls in low-level designs (e.g., power rail ordering dependencies, watchdog timeout misconfiguration, voltage threshold hysteresis). Can express designs in sufficient detail (state diagrams, timing requirements, register-level sequences) for rapid, correct implementation
• Expert-level use of embedded debugging tools (JTAG, on-target debugging, logic analyzers) to verify low-level hardware-software interactions and timing-critical behavior
• Deep understanding of Real-Time Operating Systems — FreeRTOS and/or SafeRTOS: task lifecycle, inter-task synchronization, interrupt handling, timing constraints, and periodic task patterns. Comfortable reasoning about task preemption, priority inversion, and stack requirements
• Direct experience developing drivers for safety-critical integrated circuits (PMIC, voltage supervisor, thermal sensor, or equivalent) from datasheet: SPI/I2C protocol implementation, register-level configuration, fault handling, and diagnostic integration
• Foundational knowledge of ISO 26262 ASIL-B/C functional safety concepts — safe-state strategies, diagnostic coverage, hardware/software fault tolerance allocation, and traceability. Ability to map code behavior to safety requirements without constant guidance

Nice To Haves

• Direct experience with TDA4 / J784S4 (Jacinto 7) or other TI automotive SoCs — familiarity with TI PSDK, SDL (Safety Diagnostic Library), register maps, and peripheral architecture significantly accelerates ramp-up
• Expertise in Linux-based embedded software development including gtests, Python scripting, Bazel build system, and Docker containerization for embedded CI/CD
• Prior involvement in ISO 26262 functional safety audits or certification — experience with Jama requirements traceability, FMEA/HARA, and safety case argumentation
• Experience with hardware diagnostic frameworks — LBIST (Logic BIST), PBIST (Programmable BIST), ECC integration, or other ISO 26262 diagnostic mechanisms
• Proficiency with advanced embedded debugging tools — Tracealyzer for RTOS visualization, logic analyzers for protocol decoding, or in-circuit emulators
• Prior automotive or safety-critical domain experience — body control, powertrain, medical devices, industrial control, or aerospace/defense

Responsibilities

• Own the end-to-end architecture of hardware safety and power management systems: design safe-state strategies, power sequencing across multiple cores and PMICs, thermal throttling, and watchdog orchestration. Your designs must meet ASIL-B/C safety goals
• Implement low-level drivers and firmware for safety-critical integrated circuits (PMIC, voltage supervisor, thermal monitor) directly from datasheets and the TDA4 Functional Safety Manual. These drivers run on bare metal and FreeRTOS; they must be bug-free and testable
• Lead the development of hardware-software safety diagnostic frameworks — integrate TI Safety Diagnostic Library (LBIST, PBIST, ECC, DCC, ESM) into the firmware; ensure diagnostic coverage maps to ISO 26262 hardware fault metrics; mentor engineers on coverage traceability
• Consistently perform deep-dive code reviews across all hardware safety modules. Ensure PRs are simple, bug-free, and adhere to unified architectural vision (clean driver interfaces, consistent error handling, testable design patterns). Root out assumptions that could lead to latent ASIL-rated failures
• Serve as the SME for hardware-firmware-safety interfaces. Navigate ambiguity in hardware requirements (PMIC sequencing, watchdog timing, thermal limits, voltage thresholds). Mediate disagreements in technical approach through evidence-based influence and clear understanding of safety constraints
• Mentor engineers on embedded safety patterns — code review discipline, hardware driver architecture, RTOS integration, ISO 26262 traceability, and functional safety reasoning. Build capability across the team

Benefits

• Competitive compensation packages
• High-quality individual and family medical, dental, and vision insurance
• Health savings account with available employer match
• Employer-matched 401(k) retirement plan with immediate vesting
• Employer-paid group term life insurance and the option to elect voluntary life insurance
• Paid parental leave
• Paid medical leave
• Unlimited vacation
• 15 paid holidays
• Daily lunches, snacks, and beverages available in all office locations
• Pre-tax spending accounts for healthcare and dependent care expenses
• Pre-tax commuter benefits
• Monthly wellness stipend
• Adoption/Surrogacy support program
• Backup child and elder care program
• Professional development reimbursement
• Employee assistance program
• Discounted programs that include legal services, identity theft protection, pet insurance, and more
• Company and team bonding outlets: employee resource groups, quarterly team activity stipend, and wellness initiatives

What This Job Offers

• Job Type: Full-time
• Career Level: Senior