Senior Electrical Engineer — Signal & Power Integrity

Lockheed Martin•Orlando, FL

23h•Hybrid

About The Position

You will be the Senior Signal Integrity / Power Integrity Electrical Engineer responsible for ensuring the electrical performance of high-speed and mixed-signal printed circuit board assemblies across MFC programs. The engineer performs pre- and post-layout SI/PI analysis, defines PCB stack-ups and routing constraints, supports board sign-off, and partners with program design teams as a recognized subject-matter expert. This role contributes to the MFC SI Center of Excellence and helps establish design standards, modeling flows, and best practices that scale across the Circuit Card Design portfolio.

Requirements

Bachelor's degree in Electrical Engineering (or closely related technical discipline) from an accredited institution.
5+ years of professional experience in signal integrity, power integrity, high-speed digital PCB design, or closely related electrical analysis role.
Hands-on, demonstrated experience with at least one industry SI/PI tool suite: Siemens HyperLynx, Ansys (SIwave / HFSS / Q3D), or Cadence Sigrity (PowerSI, PowerDC, Sigrity SI).
Demonstrated experience performing pre- and post-layout SI/PI analysis with documented sign-off responsibility on PCB designs.
Working knowledge of PCB stack-up design, controlled-impedance routing, and power distribution network (PDN) design.
Experience with at least one high-speed interface family: DDR3/4/5, PCIe (Gen3 or above), SerDes (≥10 Gbps), Ethernet (1G+), or USB 3.x.
U.S. Citizenship is required.
Ability to obtain a Secret security clearance.

Nice To Haves

Master's degree in Electrical Engineering with focus on signal integrity, electromagnetics, RF, or high-speed digital design.
8+ years of SI/PI experience in defense, aerospace, semiconductor, or high-reliability commercial electronics.
Hands-on experience with the Siemens Xpedition EDA flow — schematic capture, constraint-management, layout integration with HyperLynx.
Strong familiarity with IBIS / IBIS-AMI modeling, model extraction, and model validation.
Lab measurement experience with VNA (≥40 GHz), TDR, BERT, real-time scopes (≥20 GHz), and high-bandwidth differential probing techniques.
Knowledge of EMI/EMC pre-compliance analysis and design practices for mil-aero environments.
Familiarity with MIL-STD-461 (EMI/EMC), MIL-STD-810 (environmental), MIL-STD-704/1275 (power quality) or equivalent customer electrical standards.
Cross-domain co-design experience (thermal, mechanical, RF).
Demonstrated experience mentoring junior engineers or supporting technical working groups.
Active Secret clearance

Responsibilities

Perform pre-layout SI/PI analysis on high-speed interfaces (DDR, PCIe, SerDes, Ethernet, USB) — channel modeling, eye-diagram and jitter budgets, termination strategy.
Define and review PCB stack-ups, controlled-impedance and length-matching rules, and via/breakout strategies in coordination with PCB designers.
Perform post-layout SI/PI verification including S-parameter extraction, IBIS-AMI link simulation, eye-diagram/eye-mask sign-off, and crosstalk/SSO analysis.
Develop and validate PDN designs — decoupling networks, plane resonance, DC IR-drop, and AC impedance — meeting voltage tolerance and noise budgets.
Support lab measurement and correlation: VNA, TDR/TDT, BERT, high-bandwidth oscilloscope probing, eye-diagram capture, PDN impedance measurement.
Contribute to MFC design standards, guidelines, and reusable IP — author internal design rules, modeling templates, and best-practice guides.
Mentor junior engineers and serve as the SI/PI point of contact during design reviews from concept through verification.