Senior EDA Tools Hardware Engineer

Intel•Hillsboro, CA

6d•Hybrid

About The Position

Join Intel's mission to engineer world-changing technology as a Senior EDA CAD / Tool Flow Development Engineer. We are seeking an experienced engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies. This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows. The ideal candidate has strong expertise in SPICE-based characterization, Liberty model generation, custom macro timing behavior, and large-scale automation using industry-standard tools such as Synopsys NanoTime and Cadence Liberate.

Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field, with 6+ years of relevant experience.
Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 4+ years of relevant experience.
Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 2+ years of relevant experience.
3+ years of experience with Timing characterization methodologies in one of the following: (i.e. Nanotime, Liberate, or PrimeLib).
Experience with Liberty timing models.

Nice To Haves

SPICE simulation
CMOS circuits
Memory architecture fundamentals
STA fundamentals
Advanced-node custom IP or memory characterization flows
Scripting and automation skills in Linux environments

Responsibilities

Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows.
Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes.
Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
Support and enhance platforms, databases, scripts, and tools used for design automation.
Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development.