Senior ECAD Library Engineer, Platforms Infrastructure

Google•Sunnyvale, CA

About The Position

As an ECAD Librarian, you will manage the Digital Network Architecture (DNA) of our hardware, building and organizing the libraries that allow our engineers to design the world’s most powerful computing infrastructure. From large Ball Grid Array (BGA) packages to interconnects, you will ensure that every component is built for precision, manufacturability, and global scale. In this role, you will bridge the gap between Electrical Engineering, Printed Circuit Board Layout, and Manufacturing. You will architect a library system that supports seamless routing and hardware lifecycles. Your work ensures that Google’s custom-built servers move from concept to high-volume manufacturing, directly impacting the infrastructure that powers services for millions of users. Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related technical field, or equivalent practical experience.
4 years of experience developing libraries for Cadence schematic and PCB design software (e.g., Concept HDL, Allegro).
Experience with STEP file integration into the library.
Experience developing symbols and footprints for BGA packages, high-density connector, and with alt symbols and alt footprints.
Experience working within IPC standards for padstacks, footprints, and naming conventions.
Experience with DFx principles for PCB manufacturing, assembly, and test.

Nice To Haves

Experience with PCB Layout.
Experience with Allegro SKILL, Python, and Windows command line programming.
Experience with Git for revision control.

Responsibilities

Manage the library, build footprints and symbols, organize Part Table File (PTF) tables, and continually improve the library setup and structure.
Support Electrical Engineering and PCB layout based on the view point of the library such as pin/part arrangement for schematic drawing, reasonable routing, and package keepout.
Work with manufacturing and component engineers to create common footprints for non-identical parts.