Senior Digital Design Engineer - High-Speed I/O and Photonics
About The Position
The mixed-signal high-speed I/O group delivers innovative PHY designs that power the most powerful AI systems in the world today. Our portfolio includes PHY IPs and Chips for both copper and fiber channels, supporting NVIDIA's high-performance interconnect protocols: NVLINK, Ethernet, and InfiniBand. We recently delivered the industry's first 200G MRM-based silicon photonics chip, revolutionizing high-performance networking and enabling the era of Co-Packaged Optics (CPO) for NVIDIA. We enable groundbreaking technology that continually pushes the limits of wireline communication!
Requirements
- B.S. or M.S. degree in Electrical Engineering or equivalent experience.
- 5+ years of experience in high-speed digital design, proficient with front-end design flow and tools.
- Deep understanding of Verilog or System Verilog, logic design concepts, and typical structures.
- Good understanding of design for test, timing constraints, and static timing analysis.
- Experience with industry verification methodologies, such as UVM.
Nice To Haves
- Knowledge of optical transceiver devices and integrated components such as modulators, detectors, and TIAs.
- Experience with SerDes architecture and building blocks such as CDR, DFE, CTLE, TXFIR.
- Experience with digital assist analog designs, such as calibrations.
- Familiarity with mixed-signal circuit design concepts and experience in behavior modeling of mixed-signal circuits.
- Knowledge of physical layer and communication protocols, such as Ethernet, InfiniBand, PCIe, and USB.
- Understanding of on-chip microcontrollers and standard peripherals, with exposure to hardware and firmware co-design.
Responsibilities
- Working on a wide range of high-speed, powerful DSPs, silicon photonics IPs, and chips.
- Participating in chip-level features, programming model and application interface definitions.
- Collaborating closely with analog designers and system architects to develop micro-architecture specifications, calibration and adaptation algorithms, which then will be translated into RTL and firmware designs.
- Defining, building synthesis constraints and driving timing closure.
- Evaluating PPA trade-offs based on synthesis and P&R feedbacks.
- Actively participating in silicon bring-up, building testing scripts for debugging, characterization, performance tuning, and production.
- Working with cross-functional teams to ensure successful production.
Benefits
- equity
- benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Associate degree
