Senior Digital Design Engineer

NXP Semiconductors • Austin, TX

2d

About The Position

The AI Chip Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking. The Austin Digital IP team develops components for DDR, Display Controller, high-speed serial links, cores, memory controllers, and interconnect. This role involves reviewing IP architecture specifications, features, and programming models, as well as microarchitecture and interface specifications. The engineer will plan IP documentation and design, providing schedule assessments. The core of the role is to design IP meeting requirements for quality and performance using Verilog and System Verilog RTL, and vendor and internal checking tools. Collaboration with the verification team is crucial for developing test plans and achieving 100% coverage, adhering to NXP's standard quality and maturity standards. The engineer will deliver completed IP, including RTL design and supporting documentation, and track metrics during IP development, such as development plan milestones, code and functional coverage, defect tickets, and requirement tracing. A key aspect is collaborating with cross-functional teams to provide expert support to subsystem, SoC, validation, and applications engineering teams during product development. Key challenges include proving design meets all requirements, ensuring zero defects escape to silicon, and meeting committed schedules without compromising quality.

Requirements

• Minimum BSEE/BSCE/BSCS
• Minimum 4 years of experience in IP or SoC design
• Knowledge of SoC architecture required
• Expert knowledge of Verilog required
• Experience with design quality checks, including Lint, clock domain crossing (CDC) analysis, static timing analysis (STA)

Nice To Haves

• Expert knowledge of ARM AMBA bus protocol standards desired
• Knowledge of functional safety, including ISO26262 a plus
• Knowledge of CPU or cache architecture a plus
• Knowledge of C coding a plus
• Knowledge of scripting, such as Perl or Python, a plus

Responsibilities

• Review IP architecture specifications, features and programming model, microarchitecture and interface specifications.
• Plan IP documentation and design, including providing schedule assessments.
• Design IP meeting requirements for quality and performance, using Verilog and System Verilog RTL, and vendor and internal checking tools.
• Collaborate with verification team to develop test plans and complete verification execution to 100% coverage, and as per NXP standard quality and maturity standards.
• Deliver completed IP, including RTL design and supporting documentation.
• Track metrics during IP development, include development plan milestones, code and functional coverage, defect tickets, and tracing of requirements versus design specification.
• Collaborate with cross-functional teams to provide expert support to subsystem, SoC, validation, and applications engineering teams during product development.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree