Senior Digital Design Engineer, HBM

Micron • Richardson, TX

1d

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. Micron is proud to be an equal opportunity workplace and is an affirmative action employer. Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

Requirements

• RTL implementation in Verilog/SystemVerilog
• Micro-architecture definition for digital logic blocks (FSMs, datapaths, FIFOs, pipelines, arbitration logic)
• Analysis of tradeoffs across area, power, latency, and throughput
• CDC/RDC analysis
• Clocking and reset strategies
• SDC constraint creation and debugging
• Timing report interpretation
• Low-power design methodologies (CPF/UPF, clock gating, multi-domain partitioning, isolation/level shifter strategies)
• Collaboration with verification, DFT, physical design, and CAD teams

Nice To Haves

• AI-Enabled tools to assist with every day execution.

Responsibilities

• Drive all stages of the digital design flow, including concept definition, specification, RTL implementation, verification support, documentation, and post‑silicon debug.
• Develop high‑quality RTL in Verilog/SystemVerilog using scalable, parameterized design techniques aligned to architectural specifications.
• Define and refine micro‑architecture for digital logic blocks, including FSMs, datapaths, FIFOs, pipelines, and arbitration logic.
• Analyze tradeoffs across area, power, latency, and throughput, providing clear documentation and communication of design decisions.
• Utilize AI-Enabled tools to assist with every day execution.
• Perform CDC/RDC analysis, apply sound clocking and reset strategies, and identify early timing challenges.
• Support synthesis and static timing analysis by creating and debugging SDC constraints, and interpreting timing reports.
• Apply low‑power design methodologies including CPF/UPF, clock gating, multi‑domain partitioning, and isolation/level shifter strategies.
• Collaborate with verification, DFT, physical design, and CAD teams to ensure robust design closure and high coverage, including scan/ATPG readiness and functional/formal verification support.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed