Senior Design Verification Engineer (eInfochips Inc)

Arrow Electronics•US-MN-Minnesota (Remote Employees), MN

22h•Onsite

About The Position

eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. This role involves verification at the system/subsystem level, using SystemVerilog/UVM and C-based testing, with emulation capabilities. The focus is on new co-processing subsystems including NPU, MMU, SRAM, and AXI, as well as memory subsystem interactions, DSP/signal processing, and C-based test development. The engineer will utilize emulation platforms like Cadence Palladium and potentially model analog/digital interactions using Real Number Models (RNM).

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl).
Hands-on experience with UVM (Universal Verification Methodology).
Deep understanding of constrained-random verification, assertions (SVA), and functional coverage.
Knowledge of common protocols like AMBA (AXI/AHB/APB).
Strong DV fundamentals.
Experience with MMU verification.
Experience with SRAM/memory subsystem verification.
Experience with bus protocols (AXI).

Nice To Haves

Experience with formal verification tools and methodologies.
Background in power-aware verification using UPF/CPF.
Experience verifying custom ARM or DSP processor cores.
Familiarity with emulation platforms like Palladium.
DSP verification experience.
Modeling (RNM / behavioral models).

Responsibilities

Build scalable verification environments using UVM and SystemVerilog.
Create detailed verification plans from architectural specifications.
Write, run, and debug constrained-random tests and directed tests.
Define, measure, and close functional and code coverage metrics.
Run gate-level simulations to verify power-up and timing states.
Develop scripts to automate regression runs and triage failures.
Perform verification at system/subsystem level, using SV/UVM + C-based testing, with emulation (Cadence Palladium).
Verify new co-processing subsystems (with NPU, MMU, SRAM, AXI).
Verify memory subsystem interactions.
Conduct DSP/signal processing verification.
Develop C-based tests for processor-in-loop simulation.
Utilize emulation platforms (Cadence Palladium or similar).
Perform modeling using Real Number Models (RNM) for analog/digital interaction.