Senior Design Engineer

Micron Technology • San Jose, CA

2d • Onsite

About The Position

As a Sr. or Staff Design Engineer in the NVE Design Engineering Core group at Micron Technology, Inc., you will contribute to the development of memory products that are outstanding, using your specialized knowledge and Micron proprietary methods of designing and analyzing core and mixed circuits used in the development of memory products! What’s Encouraged Daily! Develop array waveforms with detailed timing and biasing conditions of array signals for conventional NAND Flash operation as well as Compute‑in‑Memory (CIM) / near‑memory compute modes. This requires in‑depth familiarity with NAND Flash read, program and erase algorithms, and how array‑level biasing, sensing, and accumulation mechanisms can be reused or extended for in‑memory compute (e.g., analog MAC, resistive summation, multi‑level sensing). Collaborate with Firmware team, Analog team and Design validation teams during actual implementation of waveforms. Plan the wordline and bitline path architecture according to area, performance and power specifications. Determine the placement of these circuit blocks and collaborate with project teams in integrating these circuit blocks to the chip plan. Perform die size cost and benefits analysis of new array circuits and algorithms prior to implementation. Working closely with other functional teams to evaluate, analyze, and improve NAND power consumptions. Generate Xpath, Ypath and Array schematics during project execution and work with project teams integrating the Core schematics into the fullchip schematics. Run block level simulations of the circuits using spice simulator and oversee layout implementation of the circuits. Run subsystem and fullchip simulations during project execution. Build and maintain Python-based AI utilities that interface with EDA environments to accelerate design tasks such as environment setup, corner execution, regression runs, automated documentation and intelligent/predictive design/layout techniques. Review existing and generate new technical documentation. Support pathfinding and prototype efforts exploring emerging CIM use cases such as vector operations, reduction, classification primitives, or AI/ML acceleration directly in the memory array, including interaction with system and algorithm teams to define viable compute primitives. Work with and support groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to enable manufacturable and testable CIM features, and to help evaluate system‑level value, cost, quality, reliability, and time‑to‑market impacts.

Requirements

• MS in electrical engineering required.
• 4+ years of NAND design relevant proven experience required with prior CIM projects led or contributed.
• A high level of self-motivation.
• Good fundamentals in semiconductor and device physics and analog/mixed-signal circuit design.
• An understanding of semiconductor reliability issues including CHC, NBTI, stress, and snapback, as well as Electro-migration (EM) and IR analysis.
• Strong circuit debugging and problem-solving skills.
• Experience of circuit verification and optimization, layout planning, parasitic extractions of the circuits, experience guiding layout.
• Strong coding skills in Python (plus Bash/Tcl a bonus), and comfort working with structured data (CSV/JSON/SQLite) and version control.

Nice To Haves

• Ph.D. preferred
• Knowledge of analog and digital simulators such as HSPICE, Fast SPICE, and Verilog
• Familiarity with Cadence design, LVS/DRC tools (a plus).
• Experience with a scripting language.
• Familiarity with Linux/UNIX

Responsibilities

• Develop array waveforms with detailed timing and biasing conditions of array signals for conventional NAND Flash operation as well as Compute‑in‑Memory (CIM) / near‑memory compute modes.
• Collaborate with Firmware team, Analog team and Design validation teams during actual implementation of waveforms.
• Plan the wordline and bitline path architecture according to area, performance and power specifications.
• Determine the placement of these circuit blocks and collaborate with project teams in integrating these circuit blocks to the chip plan.
• Perform die size cost and benefits analysis of new array circuits and algorithms prior to implementation.
• Evaluate, analyze, and improve NAND power consumptions.
• Generate Xpath, Ypath and Array schematics during project execution and work with project teams integrating the Core schematics into the fullchip schematics.
• Run block level simulations of the circuits using spice simulator and oversee layout implementation of the circuits.
• Run subsystem and fullchip simulations during project execution.
• Build and maintain Python-based AI utilities that interface with EDA environments to accelerate design tasks such as environment setup, corner execution, regression runs, automated documentation and intelligent/predictive design/layout techniques.
• Review existing and generate new technical documentation.
• Support pathfinding and prototype efforts exploring emerging CIM use cases such as vector operations, reduction, classification primitives, or AI/ML acceleration directly in the memory array, including interaction with system and algorithm teams to define viable compute primitives.
• Work with and support groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to enable manufacturable and testable CIM features, and to help evaluate system‑level value, cost, quality, reliability, and time‑to‑market impacts.

Benefits

• choice of medical, dental and vision plans
• benefit programs that help protect your income if you are unable to work due to illness or injury
• paid family leave
• robust paid time-off program
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior