Senior Circuit Design Engineer - AI & HPC (7708)

TSMC•San Jose, CA

3d•$120,000 - $165,000•Hybrid

About The Position

Join TSMC Technology, Inc. (TTI), an innovation hub of Taiwan Semiconductor Manufacturing Company Limited (TSMC). TSMC has been a pioneer in the semiconductor industry since 1987. With teams located in San Jose, CA, and Austin, TX, TTI is dedicated to advancing semiconductor technology through expertise in physical design, memory design, analog mixed signal, power management, and groundbreaking computational AI machine learning research. Our mission is to drive the future of semiconductor innovation through unparalleled R&D and customer-focused IP. Be part of a team that shapes the next generation of technological advancements. Step into a pivotal role within our San Jose design R&D team and position yourself at the forefront of the global semiconductor industry. As a Senior Circuit Design Engineer, you will leverage TSMC's leading process technology and design enablement solutions to push the boundaries of semiconductor manufacturing. In this role, you will focus on AI and high-performance computing applications, unleashing innovation and driving next-generation advancements. You will join us in our San Jose office, operating on a hybrid work schedule with 4 days in-office.

Requirements

Master’s degree with 3+ years of relevant industry experience, or a Ph.D. demonstrating applicable academic research in VLSI design or custom circuits.
In-depth knowledge of VLSI design, digital integrated circuits, Verilog, logic design, and DFT.
Hands-on experience running SPICE simulations for custom circuits.
A collaborative mindset with a strong teamwork attitude and excellent communication skills.

Nice To Haves

Advanced knowledge of leading-edge process nodes (TSMC N7 and below), ideally with a track record of successfully delivering product tapeouts below 5nm.
Deep expertise in high-speed and low-power custom SRAM or Register File architecture and implementation.
Prior experience acting as a technical lead for customer IP products or energy-efficient AI inference/training accelerators is a significant asset.
Proficiency with memory characterization and industry-standard EDA tools.
Familiarity with scripting and automation (Perl, TCL, Python) is highly advantageous and will allow you to hit the ground running.

Responsibilities

Design custom memory circuits and architectures tailored specifically for AI and HPC applications.
Lead efforts in Power, Performance, and Area (PPA) optimization for custom SRAM circuits to align with advanced scaling advancements.
Perform comprehensive technical analysis, including Time/Power/Area improvements, Read/Write margin, Noise, and Power/Signal IR/EM analysis.
Provide supervised layout guidance, manage design characterization, and oversee methodology, verification, and final sign-off.
Collaborate closely with RTL and Physical Design (PD) teams to ensure the best IP PPA integration.
Handle compiler coding and the interpretation of testing results.