Senior Cache Coherency Architect

NVIDIA•Us, CA

About The Position

We are seeking an experienced Senior Cache Coherency Architect to join our ambitious team at NVIDIA. This opportunity allows you to be part of a world-class organization that develops scalable, low-latency, high-bandwidth coherent interconnect systems. These systems power groundbreaking NVIDIA products such as Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin. In this role, you will contribute to the architecture of cache-coherent interconnect and cache subsystems, including architecture definition, modeling, and implementation. You will collaborate with CPU, GPU, memory subsystem, and SoC architects to define coherency solutions that integrate effectively into SoC designs. The role requires close partnership with multiple IP creation and verification teams throughout the project lifecycle. This position provides the chance to create a meaningful impact across product lines ranging from consumer graphics to automotive and AI platforms.

Requirements

Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in processor design or other high-performance semiconductor designs.
Deep understanding of cache coherency, with hands-on experience in industry-standard protocols (e.g., AXI, ACE, CHI).
Experience authoring specifications and designing cache-coherent interconnects.
Strong understanding of system and memory subsystem architecture, with a focus on cache-coherent interconnect.
Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
Proficiency in C, C++, Python, and Verilog.

Responsibilities

Define consistent interconnect architecture, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache-coherency compliance.
Collaborate with architects to guarantee the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
Develop and maintain functional and performance models for the NoC fabric and IP units to assist with analysis and validation.
Collaborate with cross-functional design and verification teams (simulation, emulation, and formal) to ensure implementations align with architectural specifications.
Support silicon bring-up and post-silicon debug as needed.