Senior ASIC VLSI Synthesis and Design Engineer

Saxon GlobalSanta Clarita, CA

About The Position

We are seeking a Senior ASIC VLSI Synthesis and Design Engineer with a strong background in synthesis and timing closure for large-scale designs. The ideal candidate will have extensive experience with deep submicron technology and a proven track record in RTL coding, constraint development, gate-level simulation, STA, and power-aware synthesis. This role also requires robust post-silicon debug and validation skills, including production bring-up and failure analysis. Proficiency in scripting languages for automation and flow optimization is essential, as are excellent problem-solving and collaboration skills.

Requirements

  • Bachelor's degree with 8+ years of experience OR Master's degree with 6+ years in EE, CS, IT, or related field.
  • 8+ years of ASIC/VLSI design experience focusing on synthesis and timing closure for large-scale designs in deep submicron technology.
  • Expertise in Verilog/SystemVerilog RTL coding and constraint development for synthesis.
  • Proficiency with synthesis tools (Cadence, Synopsys, Mentor).
  • Experience with gate-level simulation, STA, and power-aware synthesis.
  • Strong post-silicon debug and validation skills, including production bring-up and failure analysis.
  • Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimization.
  • Excellent problem-solving and collaboration skills in a fast-paced environment.

Responsibilities

  • Perform ASIC/VLSI design focusing on synthesis and timing closure for large-scale designs in deep submicron technology.
  • Develop Verilog/SystemVerilog RTL code and constraint development for synthesis.
  • Utilize synthesis tools (Cadence, Synopsys, Mentor).
  • Conduct gate-level simulation, static timing analysis (STA), and power-aware synthesis.
  • Perform post-silicon debug and validation, including production bring-up and failure analysis.
  • Automate and optimize design flows using scripting languages (Tcl, Perl, Python).
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