Senior ASIC Floorplan Design Engineer

NVIDIA•Austin, TX

11d•$196,000 - $310,500

About The Position

NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers a unique opportunity to craft and influence the design and development of the next generation GPU and SoC from the early architecture development phase through the physical design phase. This role allows for real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. The team consists of exceptional people globally, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Requirements

MSEE/MSCE (or equivalent experience) with broad and deep experience in chip development.
10+ years of experience.
Experience with developing SOC, CPU, graphics, memory, and I/O sub-systems in the chip.
Ability to multi-task effectively across simultaneous projects and drive the resolution of complex technical issues among multi-disciplinary engineering teams.
Experience with physical design methodologies (flow and tools development), chip floorplan, power/clock/reset distribution, DFT, place and route, timing closure, and packaging.
Strong written, verbal, and technical communications skills to present progress and options to drive towards alignment across many multi-disciplinary teams.
Agentic AI workflows, Python, Perl and/or C++ programming language experience.

Nice To Haves

Experience in driving development of large scale ASIC floorplans for chiplet based SOC and/or CPU projects.
Strong algorithm development and programming skills.
Ability to operate optimally in environments with incomplete data, evolving requirements, and tight schedules.

Responsibilities

From the early chip definition phase, partner closely with a wide variety of multi-disciplinary teams including product managers, chip architects, ASIC design, physical design, and packaging teams to craft the chip floorplan that optimizes cost/area, performance, and power for a target market.
Drive the floorplan development and collaborate with the ASIC and Physical design teams to identify and solve area, interconnect, timing, and floorplan improvement opportunities to achieve optimal product features and cost.
Develop AI workflows and productivity tools to continually improve existing infrastructure for optimizing chip area and speed of execution.
Identify key technical and product risks and work with engineering and management teams to close on risk mitigation strategies among the options.