Senior ASIC Emulation Engineer

K2 Space • Seattle, WA

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About The Position

K2 is seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable high‑fidelity hardware/software co-development and accelerate verification cycles. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first‑generation silicon and system methodology.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC development, focused on emulation
• Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
• Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
• Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
• Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++‑based system-level testing.
• Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
• Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation teams.
• Understanding of pre- and post-silicon debug methodologies and correlation workflows.

Nice To Haves

• Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
• Experience with low-power modes and power-aware emulation.
• Experience with analog/mixed-signal behavioral models in emulation environments.
• Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit PHYs.

Responsibilities

• Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce.
• Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
• Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability.
• Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
• Support system‑level testing in emulation by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end‑to‑end workloads.
• Accelerate overall verification throughput by helping DV team run targeted and high‑value tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
• Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and assisting in HW/SW integration debug.
• Run emulation workloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues.
• Maintain and enhance automation for compile flows, regression management, and continuous integration.
• Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulation best practices.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.
• Manage interactions with external IP providers or emulation partners when needed.

Benefits

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree