Senior ASIC Emulation Engineer
About The Position
As a Senior/Lead ASIC Emulation Engineer on the ASIC team, you will drive the execution, verification, and validation of high-complexity network security processors and compute architectures on state-of-the-art emulation and FPGA prototyping platforms. In this role, you will bridge the gap between pre-silicon hardware design, firmware/software development, and post-silicon validation. You will define emulation architecture, build scalable hybrid co-emulation environments, accelerate pre-silicon software bring-up, and ensure our next-generation firewall products achieve industry-leading performance and reliability.
Requirements
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- 8+ years of hands-on experience in hardware emulation, FPGA prototyping, and ASIC verification, with a proven track record of shipping complex SoCs to production.
- Expertise with at least one major emulation platform (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce).
- Strong mastery of SystemVerilog, Verilog, C/C++, and UVM/DPI interfaces.
- Proficiency with platform debug tools (SimVision, Indago, Verdi, waveform probes, and dynamic memory readback).
- Experience developing or integrating transactors, speed adapters, and virtual/physical interfaces (e.g., PCIe, Ethernet, DDR, CXL).
- Advanced scripting skills in Python, Tcl, Perl, and UNIX shell to automate compilation, regression, and build infrastructure.
Nice To Haves
- Experience with network hardware security architectures, high-speed Ethernet protocols (10G/100G/400G), or packet-processing pipelines.
- Familiarity with Hybrid Emulation / Virtual Platforms (SystemC, TLM2.0, QEMU integration).
- Background in C/C++ driver code development, OS kernel boot processes, or firmware debug on pre-silicon platforms.
- Knowledge of pre-silicon power estimation and thermal analysis tools on emulation platforms (e.g., Joules, PowerArtist, Palladium Power Analysis).
- Strong cross-functional leadership, vendor management skills, and clear communication abilities.
Responsibilities
- Architect, bring up, and maintain enterprise-scale hardware emulation platforms (e.g., Palladium, ZeBu, Veloce) and hybrid co-emulation/virtual prototyping systems.
- Collaborate closely with ASIC Architecture, Design, Verification, and Software/Firmware teams to define pre-silicon emulation plans and execution timelines.
- Compile, synthesize, and fit multi-million/billion-gate SoC designs onto emulation hardware, performing power, timing, and capacity optimization.
- Develop and maintain transactors, rate adapters, speed adapters, and hybrid virtual interfaces (C/C++, SystemC, DPI) to connect emulation models with host software testbenches and real-world network traffic generators.
- Enable pre-silicon software development and OS/driver bring-up by executing real-world workloads, benchmarks, and regression suites on the emulator.
- Debug complex, deep-trace hardware, firmware, and protocol-level failures using advanced emulation debug features (waveform captures, readback, dynamic probes, assertions).
- Automate build, deployment, triage, and regression flows using Python, Tcl, and CI/CD pipelines to optimize model compile speed and platform utilization.
- Partner with post-silicon validation teams to reproduce and triage silicon anomalies on the emulation platform.
Benefits
- restricted stock units
- bonus
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What This Job Offers
Job Type
Full-time
Career Level
Senior
