Senior ASIC Design Verification Engineer

BLUE ORIGIN • Los Angeles, CA

1d

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! - The Senior ASIC Verification Engineer leads verification of complex digital subsystems for Space based communication ASICs. This role requires strong expertise in advanced verification methodologies, architecture understanding, and multi-functional collaboration to ensure robust, high-quality silicon.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 5–8+ years of ASIC/SoC verification experience.
• Deep hands-on expertise in System Verilog and UVM.
• Strong understanding of verification planning, assertions, and coverage closure.
• Experience verifying complex digital control and datapath logic.
• Proven debugging capability across RTL, testbench, and system interactions.
• Ability to work effectively across multidisciplinary engineering teams.

Nice To Haves

• Background in Space based communications, wireless communications, or modem/baseband hardware.
• Experience verifying LDPC/BCH/FEC blocks, framing engines, beamforming logic, or DSP pipelines.
• Familiarity with formal verification tools and methodologies.
• Experience with low-power verification, CDC/RDC verification, or reset-domain behavior.
• Knowledge of high-speed interface verification and hardware/software interactions.

Responsibilities

• Lead verification planning and execution for complex blocks or subsystems.
• Develop sophisticated UVM environments, reference models, scoreboards, protocol monitors, and assertions.
• Translate architecture and design specifications into comprehensive verification strategies and measurable coverage goals.
• Drive functional coverage closure, regression health, and verification signoff readiness.
• Identify verification gaps, corner cases, and high-risk scenarios early in the development cycle.
• Collaborate closely with design, systems, DFT, firmware, and physical design teams.
• Review testbench architecture, stimulus quality, and debug methodologies for technical excellence.
• Mentor junior engineers in verification standard processes.
• Support bring-up, emulation, prototyping, and post-silicon debug activities as needed.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion.
• Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior