Senior ASIC Verification Engineer

Hewlett Packard Enterprise • Durham, NC

1d • Hybrid

About The Position

Senior ASIC Verification Engineer This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Senior ASIC Verification Engineer Role Summary We are looking for a Senior ASIC Verification Engineer to verify complex networking ASICs at both block level and full‑chip level. This role involves creating testbenches using SystemVerilog and UVM, building high‑quality verification environments, writing directed and constrained‑random tests, debugging failures, and working closely with architecture, design, and emulation teams. The role also includes developing high‑performance C++/SystemC reference models and participating in emulation and post‑silicon validation.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of experience in ASIC or SoC verification.
• Strong hands‑on experience with SystemVerilog and UVM.
• Solid understanding of: Constrained‑random verification Directed and scenario‑based testing Coverage‑driven methodologies Assertions (SVA)
• Experience writing and optimizing C++ and/or SystemC reference models.
• Experience with emulation environments and post‑silicon debug.
• Familiarity with EDA tools for simulation, debug, coverage, waveform analysis, and formal checks.
• Strong problem‑solving skills and ability to debug complex design/testbench interactions.
• Excellent communication and teamwork skills.

Nice To Haves

• Experience verifying networking ASICs (switching, routing, packet processing, or similar) is desired.
• Accountability
• Action Planning
• Active Learning
• Active Listening
• Agile Methodology
• Agile Scrum Development
• Analytical Thinking
• Bias
• Coaching
• Creativity
• Critical Thinking
• Cross-Functional Teamwork
• Data Analysis Management
• Data Collection Management (Inactive)
• Data Controls
• Design
• Design Thinking
• Empathy
• Follow-Through
• Group Problem Solving
• Growth Mindset
• Intellectual Curiosity (Inactive)
• Long Term Planning
• Managing Ambiguity

Responsibilities

• Develop verification plans for block‑level and full‑chip features based on architecture and design specifications.
• Build UVM‑based verification environments in SystemVerilog.
• Write constrained‑random tests, directed tests, and coverage‑driven tests.
• Drive functional coverage, code coverage, and closure of verification metrics.
• Run simulations, triage failures, and work closely with RTL designers to debug issues.
• Review micro‑architecture and RTL to identify corner cases and test gaps.
• Create checkers, scoreboards, assertions, and coverage models.
• Develop high‑performance C++ and SystemC reference models for key datapath or control‑plane functions.
• Integrate reference models into simulation environments for accurate checking.
• Optimize models for simulation performance and scalability.
• Develop test benches and test cases for emulation platforms (e.g., Palladium, Veloce, ZeBu).
• Work with emulation engineers to debug emulation failures and improve pre‑silicon quality.
• Support post‑silicon bring‑up, test execution, and bug root‑causing.
• Collaborate daily with architecture, RTL design, physical design, and firmware teams.
• Document verification plans, testbench architecture, and test results clearly.
• Mentor junior verification engineers and promote best practices.

Benefits

• We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Ph.D. or professional degree