Senior ASIC Design Verification Engineer

NVIDIA•Santa Clara, CA

2d•$136,000 - $218,500•Hybrid

About The Position

NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence performance of the next generation GPU and SoC, allowing you to have real impact in a multifaceted, technology-focused company with product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of highly motivated people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Requirements

BSEE (or equivalent experience) with 5+ years' experience in unit level or sub-system level verification or MS preferred in Electrical, Computer Engineering with 3+ years’ experience in unit level or sub-system level verification.
Proficiency in Object Oriented Programming, Verilog, System Verilog, UVM, SVA and functional coverage development.
Strong skills with VCS or equivalent simulation tools like Questa is required.
Strong debugging and analytical skills are required.
Have a continuous improvement mentality and passionate about delivering bug-free first silicon.

Nice To Haves

Proficiency in developing and implementing agentic AI workflows using LLMs, Skills and industry standard agentic frameworks.
Strong knowledge or work experience in custom designed IPs solutions with good understanding of behavioral real number modeling of low level digital or mixed signal designs.
Strong knowledge or work experience in co-simulation environments such as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains.
Strong interpersonal skills and ability to work with on-site and remote teams.
Proficiency in scripting language, such as, Perl, Tcl, Make files and automation methods/algorithms a certain plus.

Responsibilities

Work as part of Circuit Solutions Group to develop various innovative IPs for hardware security, clocking, voltage regulation and silicon correlation.
Own the unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced verification tools, flows and methodologies.
Build and reform world class verification infrastructure and methodologies to meet the unique demands of custom designed IPs.
Engage in design specification development by participating in discussions on architecture, intent, and implementation of the various IPs.
Enable system level integration by working with partner teams for test development & debug and delivering Verification IPs.
Play a key role in development and deployment of agentic AI frameworks for DV workflows such as stimulus generation, regression triage, debug, root cost analysis etc...