Senior ASIC Design Engineer - Terawave

BLUE ORIGIN•San Diego, CA

2d•$230,398 - $322,557•Onsite

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. We are seeking ASIC/SOC Design Validation engineers (all levels including Senior, Principal, Senior Principal) to work in the Design Validation team who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly validated cutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Requirements

Highly skilled verification engineer with extensive experience across the full spectrum of pre-silicon and post-silicon verification for complex SoC designs
Strong expertise in System Verilog, DSP structures, modem SOCs, and interface protocols
BS, MS in Electrical Engineering or a related technical field
8+ years of experience
Deep working knowledge and hands on experience in innovative verification flows

Responsibilities

Driving verification methodologies
Managing test planning and coverage closure
Ensuring seamless portability across multiple verification environments including emulation, FPGA, and silicon bring-up
Integrating and verifying complex IPs
Supporting software co-simulation across all platforms
Pre-Silicon System Verilog experience in verifying complex SOCs
Formal verification
Functional coverage, definition and collection
Module verification
Complex subsystem verification
Complex SOC verification
Co-simulation with software, integration of software build tool flow with simulation
Test planning and tracking, coverage closure
Methodology and flow, definition and implementation
Power estimation
Gate simulation
Performance analysis
External IP integration
AXI bus complex
High performance NOC and DMA
DDR, PCIE, Ethernet, SPI
High speed SERDES
DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface)
Modern modem SOCs using innovative DSP, coding, framing (phy and MAC)
Sequenced and time bound data movement in DSP structures (time slots, time stamps etc.)
AMS verification
SOC top level verification using models for analog macros
Verification using golden reference models in MATLAB, SystemC or C
Code coverage
Emulators: qualification for release, compatibility of test cases, reproduce and debug failures, how to partition verification and assess coverage between this and simulation
Portable verification across block level and top level, FPGA and ASIC, rtl and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently
Post silicon bring up
Support for post-silicon and FPGA in the same pre-silicon environment (portable bench/sim platforms).
Compatibility of test cases, reproduce and debug failures, accelerate software development
FPGA ASIC to/from FPGA flow
Prototyping: qualification for release, different design configurations and top levels, compatibility of test cases, reproduce and debug failures, accelerate software development, how to partition verification and assess coverage between this and simulation