Senior Analog IP Integration, Power, and SI Engineer

Intel Corporation•Hillsboro, OR

2d•$164,470 - $232,190•Hybrid

About The Position

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. We are seeking an experienced Analog Design Engineers to join our engineering team. The successful candidate will be responsible for designing, developing, and optimizing IP floor plans, bump maps, power delivery schemes for IP implementations in various applications. This role requires technical expertise in analog circuit design and the ability to lead complex projects from concept to production. In this role, you will drive the definition, design, and verification of high-performance analog blocks, IP top level designs and subsystems (floor planning, power delivery, bump maps), collaborating closely with system architects, logic designers, and layout engineers. The ideal candidate is self-driven, detail-oriented, and passionate about analog design in high-speed IO and die-to-die systems. You will facilitate technical discussions, hold design reviews, and play an active role in post-silicon validation and performance optimization. The position also involves providing guidance to layout engineers and mentoring junior analog designers as needed. Strong problem-solving skills, teamwork, and a willingness to share knowledge and collaborate across disciplines are essential. This role offers an opportunity to develop innovative designs and be part of a highly experienced IO and die-to-die design team focused on delivering next-generation high-speed interconnect solutions.

Requirements

Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 5+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications.
Proven experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter (TX), Power Delivery design, IP floor planning, IP top level performance simulation, signal integrity analysis.
Background in high-speed IO calibration and training algorithms.
Familiarity with high-speed communication standards such as UCIE and PCIe (Gen5/Gen6/Gen7).
Core analog design principles, including noise, linearity, matching, and stability.
Hands-on experience with advanced FinFET CMOS process technologies.
Analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
Post-silicon validation, lab measurements, and debug of analog circuits.
Good communication and documentation skills, with a collaborative and proactive work style.
Demonstrated ability to work effectively in cross-functional, global teams and contribute to technical reviews.
Strong analytical thinking, hands-on debugging skills, and an eagerness to learn and share expertise within the team.

Nice To Haves

Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline with 4+ years of experience in analog design for high-speed SerDes and/or die-to-die applications.
Power Delivery design, IP floor planning, IP top level performance simulation OR signal integrity analysis would be considered preferred
In-depth understanding of transmitter and receiver design, CDR loops, and equalization techniques.
Exposure to next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD.
Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl).
Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis.
Background in standard and advanced package technologies.

Responsibilities

Design and simulate analog and mixed-signal circuits including amplifiers, data converters, voltage regulators, PLLs, and other analog building blocks.
Develop circuit architectures and perform detailed transistor-level design.
Create and optimize layouts working closely with layout engineers.
Perform circuit analysis, simulation, and verification using industry-standard tools (Cadence, Synopsys, etc.) using approaches that enable automation and take advantage of available AI-supported solutions.
Lead analog design projects from specification to silicon validation.
Mentor junior engineers and provide technical guidance.
Collaborate with cross-functional teams including architecture, logic, verification, physical design, layout, post-silicon manufacturing and validation teams, and SOC partners.
Drive design reviews and ensure adherence to design methodologies.
Facilitate design development and convergence across global teams designing concurrently in numerous process nodes.
You will be expected to work with teams in the US and India to ensure design interoperability and solve problems to deliver designs that meet quality and KPI goals.
Develop test plans and oversee silicon characterization.
Debug and resolve design issues during pre and post-silicon phases.
Optimize designs for performance, power, and area requirements.
Ensure designs meet specifications and industry standards.