Senior AI System Architect

Credo•San Jose, CA

2d•Onsite

About The Position

Team Credo is looking for a Senior AI System Architect to join our team in San Jose, CA, reporting to AVP, XPU system AI interface. This role needs to solve the system-level interconnection challenges that connect XPUs (NPU/GPU/custom silicon) into working AI infrastructure. This role needs to follow and define how compute elements are wired, networked, and orchestrated together at node, rack, and cluster scale so that large-scale LLM training and inference run efficiently across the platform. We strongly prefer candidates with a hands-on NPU hardware architect background and real experience taking NPU silicon into production deployment at scale.

Requirements

Bachelor's degree in Computer Engineering, EE, CS, or related field required.
Three years in XPU or AI interconnect system architecture and micro architecture working experience.
Strong foundational understanding of computer architecture, including GPU, NPU, and/or CPU design principles.
Familiarity with large language model architectures and distributed training/inference concepts (e.g., parallelism strategies, model serving) through coursework, research, or personal projects.
Demonstrated analytical ability — for example, through published research, thesis work, or quantitative project work — with a track record of independently studying and synthesizing technical material.
Strong cross-functional leadership and communication skills, daily experience working with compiler, software, SOC & backend team preferred.

Nice To Haves

Master's or PhD in Computer Science, Artificial Intelligence, Engineering, or a related field.
Deep, hands-on NPU hardware architecture expertise.
Real, hands-on NPU architecture background, with direct experience participating in an NPU design from architecture definition through silicon bring-up, validation, and volume production deployment.
Working knowledge of high-speed interconnect or networking concepts (e.g., PCIe, Ethernet, RDMA) is a plus.

Responsibilities

Solve the system-level interconnection challenges that connect XPUs (NPU/GPU/custom silicon) into working AI infrastructure.
Follow and define how compute elements are wired, networked, and orchestrated together at node, rack, and cluster scale so that large-scale LLM training and inference run efficiently across the platform.