Senior Advanced TIDES Engineer

M9 Solutions•Scottsdale, AZ

8d•$130,000 - $150,000•Hybrid

About The Position

M9 Solutions is seeking a Senior Digital Hardware Designer to work hybrid remote/onsite in support of a government contract for a client located in Scottsdale, AZ. An active Secret clearance is required. This role involves supporting the development, deployment, and proposal shaping of integrated spacecraft test environments across hardware, firmware, and software infrastructure. The engineer will contribute to the architecture, design, integration, and verification of various test environments, translating payload and program requirements into test capabilities and measurement approaches. Responsibilities include supporting design package development, coordinating FPGA and digital I/O needs, and supporting client internal software tool and related test infrastructure deployment. The role also involves identifying gaps in test capabilities, driving reuse across programs, and supporting proposal development. The engineer will lead or support technical solutioning discussions, drive trade studies, and translate ambiguous program needs into actionable plans. Additionally, they will support technical reviews, mentor engineers, and communicate technical issues effectively.

Requirements

Active Secret security clearance.
Bachelor’s degree in Systems Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree, plus a minimum of 6 years of relevant experience.
Experience with spacecraft payload development, integration, verification, production test, or sustainment.
Strong understanding of system test environments, automated test systems, RF test equipment, FPGA-based interfaces, rack-level integration, test data infrastructure, and networked lab environments.
Ability to work backward from payload requirements to define required stimulus, measurement, cabling, calibration, software, network configuration, and ATP evidence.
Experience with requirements analysis, requirements traceability, interface definition, system integration, verification planning, and test readiness reviews.
Experience supporting proposals, BOEs, technical volumes, basis-of-estimate narratives, labor estimates, risks, assumptions, and solution-space trades.
Ability to lead technical discussions where the problem is not fully defined and drive the team toward practical, executable options.
Experience configuring and sustaining internal test networks and lab infrastructure, including static IP planning, isolated instrument LANs, 10G data paths, server/workstation setup, software deployment, account coordination, backup/data handling, and troubleshooting of networked test equipment.
Familiarity with LabVIEW, TestStand, Python, Git, CI/CD concepts, Kubernetes or containerized deployment (docker), networked test systems, and instrument control.
Familiarity with FPGA development, high-speed digital interfaces, timing/reference distribution, JESD204B, Ethernet/10G data paths, or hardware-in-the-loop test.
Strong technical judgment across electrical hardware, software infrastructure, systems engineering, lab infrastructure, and software deployment boundaries.
Demonstrated ability to lead technical coordination across multiple teams, resolve ambiguity, remove blockers, and drive closure on complex integration issues.
Strong problem-solving mindset with the initiative to fix issues as they arise, prevent recurring problems, and identify technical risks before they impact program execution.
Ability to leverage AI-enabled tools appropriately for engineering productivity, research, documentation, automation, analysis, and decision support while applying independent technical judgment and verification.
Strong written and verbal communication skills, including the ability to brief technical risks, trade studies, readiness gaps, and corrective actions.
Motivated to improve reuse, standardization, automation, resiliency, and long-term supportability across program test environments.

Responsibilities

Support the development, deployment, and proposal shaping of integrated spacecraft test environments across hardware, firmware, and software infrastructure.
Support architecture, design, integration, and verification of development, unit verification, production, module, power converter, NAS, and calibration test environments.
Translate payload and program requirements into test capabilities, measurement approaches, interface needs, verification methods, and evidence-generation plans.
Support design package development, including top-level assemblies, interface control documents, cable packages, rack architecture, RF drawer concepts, FPGA/IO drawer concepts, calibration planning, BOM coordination, and test readiness artifacts.
Coordinate FPGA and digital I/O needs across test racks, payload interfaces, data capture paths, timing/reference distribution, and platform evolution plans.
Support client internal software tool and related test infrastructure deployment, including station configuration, network topology, equipment monitoring, automated test execution, data handling, and reusable software core integration.
Identify gaps between payload requirements, available test capability, ATP coverage, calibration approach, and formal verification evidence.
Drive reuse across programs by identifying common capabilities that should be promoted into core infrastructure.
Support proposal development, BOE inputs, labor estimates, technical approaches, assumptions, risks, opportunities, and execution plans.
Lead or support technical solutioning discussions with program teams, capture teams, engineering leadership, and subject-matter experts.
Drive trade studies across hardware, FPGA, software infrastructure, automation, calibration, verification, schedule, cost, and risk.
Translate ambiguous program needs into candidate architectures, phased implementation plans, staffing needs, risks, and decision points.
Support technical reviews, proposal color-team responses, customer-facing discussion preparation, and internal leadership briefings.
Mentor engineers across disciplines and help establish consistent engineering practices.
Communicate technical issues, risks, impacts, and corrective actions to program teams, leadership, and internal employees.