Semiconductor Manufacturing & Architecture Analyst

SemiAnalysis•Hillsboro, OR

2d•Onsite

About The Position

SemiAnalysis is scaling STEEL, our semiconductor teardown and characterization lab in Hillsboro, Oregon, to support deep research into the hardware shaping the AI and datacenter industry. We are hiring a Competitive Analysis Engineer (Semiconductor Manufacturing & Architecture). This is a highly hands-on role focused on generating evidence-based technical insights through physical teardown, imaging, and analysis of leading-edge hardware. You will work across the full lifecycle, from sample preparation to data interpretation, translating physical observations into clear, defensible conclusions on process technology, integration strategies, and design intent. This role is ideal for individuals driven by curiosity, investigation, and technical rigor, with the ability to connect microscopic evidence to macro-level industry decisions. You will operate as a subject matter authority on current and next-generation semiconductor manufacturing for AI and datacenter systems.

Requirements

3+ years of experience in semiconductor-related roles, including: Process integration (FEOL / BEOL) Advanced packaging integration Silicon / hardware engineering OR a closely related domain with exposure to leading-edge nodes
Broad process familiarity across: CMOS logic Memory technologies (e.g., HBM, GDDR, 3D NAND) Emerging semiconductor technologies
Strong understanding of: Process integration and product architecture Design Technology Co-Optimization (DTCO) principles
Demonstrated ability to: Reason from physical / structural evidence → process & design intent Distinguish between real signals vs artifacts in analysis
Hands-on experience or strong aptitude in: Semiconductor sample preparation Analytical tools such as FIB, SEM, and related techniques
Core competencies: Strong technical writing and structured argumentation High curiosity, ownership, and investigative mindset Ability to work independently and close analytical loops end-to-end

Nice To Haves

Experience with advanced characterization techniques: X-ray FIB, PFIB SEM / TEM / STEM / EELS/ EDS / WDS SIMS / XRF / XPS
Exposure to: Advanced packaging R&D (2.5D / 3D integration, hybrid bonding, high-speed interconnects) Failure analysis & fault isolation (nanoprobing, emission microscopy, laser/e-beam methods)
Proven ability to: Interpret micrographs and compositional data to infer process/design characteristics
Programming skills: Python for image analysis, data processing, or lab automation
Established industry network across semiconductor ecosystem (foundries, memory vendors, packaging players)

Responsibilities

Conduct end-to-end teardown and characterization of AI and datacenter hardware, spanning package → die → transistor level
Perform hands-on sample preparation and analysis, including operating tools such as FIB, SEM, and related characterization equipment
Interpret imaging and analytical data to derive insights on process integration, materials, and design trade-offs
Analyze and document FEOL, BEOL, and advanced packaging trends across foundries, memory vendors, and OSATs
Identify generational technology shifts, competitive positioning, and trade-offs in manufacturing approaches
Apply Design Technology Co-Optimization (DTCO) principles to explain design/process decisions, cost implications, and performance outcomes
Produce high-quality technical research and written analysis, co-authoring publications for SemiAnalysis clients
Translate complex physical findings into clear, structured, and defensible narratives for a technical audience
Contribute to the development and expansion of lab capabilities, workflows, and analytical coverage