Security Architect, Custom Silicon

GlobalFoundries•Richardson, TX

62d

About The Position

The SoC Security Architect defines and drives the hardware security architecture for SoCs across a range of end applications, with deep expertise in hardware security and HW/SW interaction. This role focuses on High Security Module (HSM) definition and SoC-level security architecture—including secure boot, Root of Trust (RoT), cryptographic IP integration, and security-aware DFT/TEST—to ensure robust protection against evolving threats across the entire product lifecycle.

Requirements

Bachelor's or Master's degree in Electrical/Electronic/Computer Engineering or a related field.
10–15+ years of experience in SoC or MCU design with a strong focus on hardware security architecture and HW/SW interactions.
Strong understanding of SoC architecture, AMBA/AXI-class interconnects, memory subsystems, and how security policies are enforced across HW/SW boundaries.
Proven experience with threat modeling, risk assessment, security validation, and vulnerability analysis for SoC-based systems.
Hands-on background with RTL design, synthesis concepts, and EDA flows sufficient to review and guide secure implementation (even if not the primary RTL owner).
Excellent written and verbal communication skills for specifications, reviews, and stakeholder alignment.

Nice To Haves

15+ years of experience in custom silicon, ASIC, or SoC development with a track record of leading Architecture.
Expertise in secure boot, RoT concepts, cryptographic protocol usage, and security IP integration at the SoC level.
Familiarity with embedded software development and secure firmware concepts, including secure update mechanisms and runtime integrity checks.
Experience with security-focused specifications and standards such as Caliptra, DICE, or related attestation and hardware RoT frameworks.
Exposure to hardware fuzzing and software exploitation techniques.

Responsibilities

Define SoC hardware security architecture and requirements, including HSM specification, secure boot/RoT concepts, and cryptographic IP integration strategies.(AES/SHA/PKA/PUF/PQC etc)
Lead threat modeling, risk assessments, and vulnerability analysis; translate into architectural mitigations and design constraints.
Architect HW/SW security boundaries and co-design flows for secure boot, firmware services, drivers, and runtime protection.
Define secure key storage/provisioning (eFUSE/OTP) and security-aware DFT/TEST strategies balancing coverage and attack resistance.
Collaborate with architecture, RTL, verification, DFT, PD, and software teams to embed security into implementation and validation flows.
Ensure compliance with cybersecurity standards (ISO 21434), optimize for PPA trade-offs, and drive system-level security validation.
Stay current on threats/standards (Caliptra, DICE) and provide technical leadership through reviews and security guidance.
Collaborate with cross-functional teams (Architecture, RTL Design, Verification, DFT, Physical Design, Firmware/Software, Systems, Quality, and Product/Customer teams) to align security, safety, test, and product requirements and to support customer discussions, audits, and security reviews.
Ensure security, safety, and system-level design compliance in architecture, adhering to relevant standards (e.g., ISO 26262, IEC 61508).